Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-tegra-critical' and 'clk-tegra-emc-oob' into clk-next

* clk-imx-critical:
  :  - Convert to CLK_IS_CRITICAL for i.MX51/53 driver
  clk: imx51-imx53: Include sizes.h to silence compile errors
  clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICAL

* clk-tegra-bpmp:
  :  - Fix Tegra BPMP driver oops when some xlating a NULL clk
  clk: tegra: bpmp: Don't crash when a clock fails to register

* clk-tegra-124:
  :  - Proper default configuration for vic03 and vde clks on Tegra124
  clk: tegra: Make vde a child of pll_c3
  clk: tegra: Make vic03 a child of pll_c3

* clk-tegra-critical:
  :  - Mark Tegra memory controller clks as critical
  clk: tegra: Mark Memory Controller clock as critical

* clk-tegra-emc-oob:
  :  - Fix array bounds clamp in Tegra's emc determine_rate() op
  clk: tegra: emc: Avoid out-of-bounds bug

Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next

* clk-ingenic-fixes:
  :  - Ingenic i2s bit update and allow UDC clk to gate
  clk: ingenic: Add missing flag for UDC clock
  clk: ingenic: Fix incorrect data for the i2s clock

* clk-max9485:
  :  - Maxim 9485 Programmable Clock Generator
  clk: Add driver for MAX9485
  dts: clk: add devicetree bindings for MAX9485

* clk-pxa-32k-pll:
  :  - Expose 32 kHz PLL on PXA SoCs
  clk: pxa: export 32kHz PLL

* clk-aspeed:
  :  - Fix name of aspeed SDC clk define to have only one 'CLK'
  clk: aspeed: Fix SDCLK name

* clk-imx6sll-gpio:
  :  - imx6sll GPIO clk gate support
  clk: imx6sll: add GPIO LPCGs

Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', 'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next

* clk-imx6-video-parent:
  :  - Fix i.MX6QDL video clk parent
  clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL

* clk-qcom-sdm845-criticals:
  :  - critical clk markings for qcom SDM845
  clk: qcom: Enable clocks which needs to be always on for SDM845

* clk-renesas:
  clk: renesas: Renesas R9A06G032 clock driver
  dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
  dt-bindings: clock: Add the r9a06g032-sysctrl.h file
  clk: renesas: r8a7795: Add CCREE clock
  clk: renesas: r8a7795: Add CR clock

* clk-stratix10-fixes:
  :  - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents
  clk: socfpga: stratix10: fix the sdmmc_free_clk mux
  clk: socfpga: stratix10: fix the parents of mpu_free_clk

* clk-atmel-i2s:
  :  - Atmel at91 I2S audio clk support
  clk: at91: add I2S clock mux driver
  dt-bindings: clk: at91: add an I2S mux clock

Merge branches 'clk-qcom-set-rate-gate', 'clk-core-set-rate-gate', 'clk-core-duty-cycle', 'clk-si-prepare' and 'clk-imx-gpio-gates' into clk-next

* clk-qcom-set-rate-gate:
  clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks

* clk-core-set-rate-gate:
  clk: fix CLK_SET_RATE_GATE with clock rate protection

* clk-core-duty-cycle:
  clk: add duty cycle support

* clk-si-prepare:
  :  - SI544/SI514 clk on/off support
  clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations

* clk-imx-gpio-gates:
  :  - i.MX6UL GPIO clock gates in CCM CCGR
  clk: imx6ul: remove clks_init_on array
  clk: imx6ul: add GPIO clock gates
  dt-bindings: clock: imx6ul: Do not change the clock definition order

Apparently there was an attempt to avoid out-of-bounds accesses when there
is only one memory timing available, but there is a typo in the code that
neglects that attempt.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Memory Controller should be always-on. Currently the sibling EMC clock is
marked as critical, let's mark MC clock too for consistency.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The current default is to leave the VDE clock's parent at the default,
which is clk_m. However, that is not a configuration that will allow the
VDE to function. Reparent it to pll_c3 instead to make sure the hardware
can actually decode video content.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

By default, the vic03 clock is a child of pll_m but that runs at 924 MHz
which is too fast for VIC. Make vic03 a child of pll_c3 by default so it
will run at a supported frequency.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

When registering clocks, we just skip any that fail to register
(leaving a NULL hole in the clock table). However, our of_xlate
function still tries to dereference each entry while looking for
the clock with the requested id, causing a crash if any clocks
failed to register. Add a check to of_xlate to skip any NULL
clocks.
Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This driver uses sizes.h, but relies on it being implicitly included
somewhere else breaking random direct compilation of the file. Include
sizes.h so we can build it those configurations too for better compile
coverage.
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Instead of explicitly enabling critical clocks via clk_prepare_enable(),
let's use the standard CLK_IS_CRITICAL flag instead, which makes the code
a bit shorter.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

According to Reference Manual Rev.0, 06/2017, there are GPIO LPCGs
defined in CCM CCGRs, add them into clock tree.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The SDCLK was named SDCLKCLK, and no one has used this yet.
Fix it.
Signed-off-by: NLei YU <mine260309@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This clock is especially used by the RTC driver, so export it so that
devicetree users can use it.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This patch adds a driver for MAX9485, a programmable audio clock generator.

The device requires a 27.000 MHz clock input. It can provide a gated
buffered output of its input clock and two gated outputs of a PLL that can
generate one out of 16 discrete frequencies. There is only one PLL however,
so the two gated outputs will always have the same frequency but they can
be switched individually.

The driver for this device exposes 4 clocks in total:

- MAX9485_MCLKOUT:      A gated, buffered output of the input clock
- MAX9485_CLKOUT:       A PLL that can be configured to 16 different
			discrete frequencies
- MAX9485_CLKOUT[1,2]:  Two gated outputs for MAX9485_CLKOUT

Some PLL output frequencies can be achieved with different register
settings. The driver will select the one with lowest jitter in such cases.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
[sboyd@kernel.org: Use local variable for val in max9485_clkout_recalc_rate()
and shorten line of max9485_of_clk_get()]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The register field for configuring the divider for the i2s clock
occupies the bits [8-0], which means 9 bits and not 8.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This patch adds the devicetree bindings for MAX9485, a programmable audio
clock generator.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This driver is a simple muxing driver that controls the
I2S's clock input by using syscon/regmap to change the parent.
The available inputs can be peripheral clock and generated clock.
Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@microchip.com>
[sboyd@kernel.org: Fix SPDX tag comment style]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The I2S mux clock can be used to select the I2S input clock. The
available parents are the peripheral and the generated clocks.
Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@microchip.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The first parent of the sdmmc_free_clk should be the main_sdmmc_clk.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add a clock mux that is used as a parent for the mpu_free_clk.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Merge tag 'clk-renesas-for-v4.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates for v4.19 from Geert Uytterhoeven:

  - Add support for Crypto Engine clocks on R-Car H3
  - Add support for the new RZ/N1D SoC

* tag 'clk-renesas-for-v4.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Renesas R9A06G032 clock driver
  dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
  dt-bindings: clock: Add the r9a06g032-sysctrl.h file
  clk: renesas: r8a7795: Add CCREE clock
  clk: renesas: r8a7795: Add CR clock

There are certain clocks which needs to be always enabled for system
operation. Add support for the same by adding 'CLK_IS_CRITICAL' flag
for such clocks.
Signed-off-by: NAmit Nischal <anischal@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

q/dl datasheets list the 5th selection value for ck01_sel as
video_27M_clk_root.

By replacing the dummy value we then can set IMX6QDL_CLK_VIDEO_27M
as parent for IMX6QDL_CLK_CKO1_SEL.
Signed-off-by: NPhilipp Puschmann <pp@emlix.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.

ARM clock is busy divider type which has the
CLK_IS_CRITICAL flag set by default when registered.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

i.MX6UL has GPIO clock gates in CCM CCGR,
add them into clock tree for clock management.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Commit f5a4670d ("clk: imx: Add new clo01 and clo2 controlled
by CCOSR") introduced the CLK_CLKO definitions, but didn't put them
at the end of the list, which may cause dtb breakage when running an old
dtb with a newer kernel.

In order to avoid that, simply add the new CLK_CKO clock definitions
at the end of the list.

Fixes: f5a4670d ("clk: imx: Add new clo01 and clo2 controlled by CCOSR")
Reported-by: NStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This adds prepare/unprepare/is_prepared functionality to the drivers for
the SI544 and SI514 chips, allowing the clock output to be disabled when
the clock is not in use.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This provides a clock driver for the Renesas R09A06G032.
This uses a structure derived from both the R-Car Gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: NMichel Pollet <michel.pollet@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The Renesas R9A06G032 SYSCTRL node description.
Signed-off-by: NMichel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This adds the constants necessary to use the renesas,r9a06g032-sysctrl node.
Signed-off-by: NMichel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add the possibility to apply and query the clock signal duty cycle ratio.

This is useful when the duty cycle of the clock signal depends on some
other parameters controlled by the clock framework.

For example, the duty cycle of a divider may depends on the raw divider
setting (ratio = N / div) , which is controlled by the CCF. In such case,
going through the pwm framework to control the duty cycle ratio of this
clock would be a burden.

A clock provider is not required to implement the operation to set and get
the duty cycle. If it does not implement .get_duty_cycle(), the ratio is
assumed to be 50%.

This change also adds a new flag, CLK_DUTY_CYCLE_PARENT. This flag should
be used to indicate that a clock, such as gates and muxes, may inherit
the duty cycle ratio of its parent clock. If a clock does not provide a
get_duty_cycle() callback and has CLK_DUTY_CYCLE_PARENT, then the call
will be directly forwarded to its parent clock, if any. For
set_duty_cycle(), the clock should also have CLK_SET_RATE_PARENT for the
call to be forwarded
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180619144141.8506-1-jbrunet@baylibre.com

CLK_SET_RATE_GATE should prevent any operation which may result in a rate
change or glitch while the clock is prepared/enabled.

IOW, the following sequence is not allowed anymore with CLK_SET_RATE_GATE:
* clk_get()
* clk_prepare_enable()
* clk_get_rate()
* clk_set_rate()

At the moment this is enforced on the leaf clock of the operation, not
along the tree. This problematic because, if a PLL has the CLK_RATE_GATE,
it won't be enforced if the clk_set_rate() is called on its child clocks.

Using clock rate protection, we can now enforce CLK_SET_RATE_GATE along the
clock tree
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Tested-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180619134051.16726-3-jbrunet@baylibre.com

the mmci driver (drivers/mmc/host/mmci.c) does the following sequence:
* clk_prepare_enable()
* clk_set_rate()

on SDCx_clk which is a children of SDCx_src. SDCx_src has
CLK_SET_RATE_GATE so this sequence should not be allowed but this was not
enforced. IOW, the flag is ignored. Dropping the flag won't change
anything to the current behaviour of the platform.

CLK_SET_RATE_GATE is being fixed and enforced now. If the flag was kept,
the mmci driver would receive -EBUSY when calling clk_set_rate()
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180619134051.16726-2-jbrunet@baylibre.com

This patch adds the clock used by the CryptoCell 630p instance in the
SoC.
Signed-off-by: NGilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add the CR core clock, which is used by the Secure Engine (SCEG).
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Tested-by: NGilad Ben-Yossef <gilad@benyossef.com>

Pull block fixes from Jens Axboe:
 "A collection of fixes that should go into -rc1. This contains:

   - bsg_open vs bsg_unregister race fix (Anatoliy)

   - NVMe pull request from Christoph, with fixes for regressions in
     this window, FC connect/reconnect path code unification, and a
     trace point addition.

   - timeout fix (Christoph)

   - remove a few unused functions (Christoph)

   - blk-mq tag_set reinit fix (Roman)"

* tag 'for-linus-20180616' of git://git.kernel.dk/linux-block:
  bsg: fix race of bsg_open and bsg_unregister
  block: remov blk_queue_invalidate_tags
  nvme-fabrics: fix and refine state checks in __nvmf_check_ready
  nvme-fabrics: handle the admin-only case properly in nvmf_check_ready
  nvme-fabrics: refactor queue ready check
  blk-mq: remove blk_mq_tagset_iter
  nvme: remove nvme_reinit_tagset
  nvme-fc: fix nulling of queue data on reconnect
  nvme-fc: remove reinit_request routine
  blk-mq: don't time out requests again that are in the timeout handler
  nvme-fc: change controllers first connect to use reconnect path
  nvme: don't rely on the changed namespace list log
  nvmet: free smart-log buffer after use
  nvme-rdma: fix error flow during mapping request data
  nvme: add bio remapping tracepoint
  nvme: fix NULL pointer dereference in nvme_init_subsystem
  blk-mq: reinit q->tag_set_list entry only after grace period

Pull documentation fixes from Mauro Carvalho Chehab:
 "This solves a series of broken links for files under Documentation,
  and improves a script meant to detect such broken links (see
  scripts/documentation-file-ref-check).

  The changes on this series are:

   - can.rst: fix a footnote reference;

   - crypto_engine.rst: Fix two parsing warnings;

   - Fix a lot of broken references to Documentation/*;

   - improve the scripts/documentation-file-ref-check script, in order
     to help detecting/fixing broken references, preventing
     false-positives.

  After this patch series, only 33 broken references to doc files are
  detected by scripts/documentation-file-ref-check"

* tag 'docs-broken-links' of git://linuxtv.org/mchehab/experimental: (26 commits)
  fix a series of Documentation/ broken file name references
  Documentation: rstFlatTable.py: fix a broken reference
  ABI: sysfs-devices-system-cpu: remove a broken reference
  devicetree: fix a series of wrong file references
  devicetree: fix name of pinctrl-bindings.txt
  devicetree: fix some bindings file names
  MAINTAINERS: fix location of DT npcm files
  MAINTAINERS: fix location of some display DT bindings
  kernel-parameters.txt: fix pointers to sound parameters
  bindings: nvmem/zii: Fix location of nvmem.txt
  docs: Fix more broken references
  scripts/documentation-file-ref-check: check tools/*/Documentation
  scripts/documentation-file-ref-check: get rid of false-positives
  scripts/documentation-file-ref-check: hint: dash or underline
  scripts/documentation-file-ref-check: add a fix logic for DT
  scripts/documentation-file-ref-check: accept more wildcards at filenames
  scripts/documentation-file-ref-check: fix help message
  media: max2175: fix location of driver's companion documentation
  media: v4l: fix broken video4linux docs locations
  media: dvb: point to the location of the old README.dvb-usb file
  ...