This patch changes the prototype of spi_nor_scan(): its 3rd parameter
is replaced by a 'struct spi_nor_hwcaps' pointer, which tells the spi-nor
framework about the actual hardware capabilities supported by the SPI
controller and its driver.

Besides, this patch also introduces a new 'struct spi_nor_flash_parameter'
telling the spi-nor framework about the hardware capabilities supported by
the SPI flash memory and the associated settings required to use those
hardware caps.

Then, to improve the readability of spi_nor_scan(), the discovery of the
memory settings and the memory initialization are now split into two
dedicated functions.

1 - spi_nor_init_params()

The spi_nor_init_params() function is responsible for initializing the
'struct spi_nor_flash_parameter'. Currently this structure is filled with
legacy values but further patches will allow to override some parameter
values dynamically, for instance by reading the JESD216 Serial Flash
Discoverable Parameter (SFDP) tables from the SPI memory.
The spi_nor_init_params() function only deals with the hardware
capabilities of the SPI flash memory: especially it doesn't care about
the hardware capabilities supported by the SPI controller.

2 - spi_nor_setup()

The second function is called once the 'struct spi_nor_flash_parameter'
has been initialized by spi_nor_init_params().
With both 'struct spi_nor_flash_parameter' and 'struct spi_nor_hwcaps',
the new argument of spi_nor_scan(), spi_nor_setup() computes the best
match between hardware caps supported by both the (Q)SPI memory and
controller hence selecting the relevant settings for (Fast) Read and Page
Program operations.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>

When nor's size larger than 16MByte, nor's address width maybe
set to 3 or 4, and controller should change address width according
to nor's setting.
Signed-off-by: NGuochun Mao <guochun.mao@mediatek.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

The quadspi is a specialized communication interface targeting single,
dual or quad SPI Flash memories.

It can operate in any of the following modes:
-indirect mode: all the operations are performed using the quadspi
 registers
-read memory-mapped mode: the external Flash memory is mapped to the
 microcontroller address space and is seen by the system as if it was
 an internal memory
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

All required stateless 4-byte op codes are supported by this flash
chip. The stateless 4-byte support can't be autodetected due to a
missing 4-byte Address Instruction Table in SFDP.

Fixes hangs on reboot for SoCs expecting the flash chip in 3byte mode.
Signed-off-by: NMathias Kresin <dev@kresin.me>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Add new Micron N25Q256A (N25Q256A11) 256Mbit NOR Flash in the list
of supported devices. This chip has the same structure as the N25Q256A
but ID and voltage (1V8) to use is different. Therefore, this adds
N25Q256A11 as n25q256ax1.

In the future, for new Micron memories we could use the patterns
"n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Macronix MX25U2033E, MX25U4033E and MX25U4035 devices are used in 4/5/6th
generation Kindle ebook readers. Both MX25U403x variants share the same
JEDEC id. Add those spi-nor variants and the similar MX25U8035 mentioned
in the same set of datasheets.
Signed-off-by: NAlexander Kurz <akurz@blala.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Winbond W25Q20BW devices are used in 4/5th generation Kindle ebook readers.
Add this spi-nor device and the similar W25Q20 devices to the list of known
devices.
Signed-off-by: NAlexander Kurz <akurz@blala.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Micron n25q00 are stacked chips, thus do not support chip erase.
>From now spi-nor framework will not send chip erase command,
instead will use sector at time erase procedure.
Signed-off-by: NMarcin Krzeminski <mar.krzeminski@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Currently it is possible to disable chip erase for spi-nor driver.
Some modern stacked (multi die) flash chips do not support chip
erase opcode at all but spi-nor framework needs to cope with them too.
This commit extends existing functionality to allow disable
chip erase for a single flash chip.
Signed-off-by: NMarcin Krzeminski <mar.krzeminski@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Fix typos and add the following to the scripts/spelling.txt:

  disble||disable
  disbled||disabled

I kept the TSL2563_INT_DISBLED in /drivers/iio/light/tsl2563.c
untouched.  The macro is not referenced at all, but this commit is
touching only comment blocks just in case.

Link: http://lkml.kernel.org/r/1481573103-11329-20-git-send-email-yamada.masahiro@socionext.comSigned-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Add support for the ESMT F25L32QA and F25L64QA.
These are 4MB and 8MB SPI-NOR Chips from Elite Semiconductor Memory
Technology.
Signed-off-by: NL. D. Pinney <ldpinney@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This fixes a sparse warning about incorrect type in return expression.
Signed-off-by: NNicholas Mc Guire <der.herr@hofr.at>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

writeable in struct intel_spi is a boolean and assignment should be to
true/false not 1/0 as recommended by boolinit.cocci.
Signed-off-by: NNicholas Mc Guire <der.herr@hofr.at>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

hisi_spi_nor_probe() ignores clk_prepare_enable() error code.
The patch fixes that.

Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: NAlexey Khoroshilov <khoroshilov@ispras.ru>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Checking for ret < 0 is redundant because a previous check on ret
being non-zero already handles the ret < 0 case. Remove the redundant
code. Found by CoverityScan, CID#1398863, CID#1398864
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Reviewed-by: NRichard Weinberger <richard@nod.at>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.
Signed-off-by: NYunhui Cui <B56489@freescale.com>
Signed-off-by: NYunhui Cui <yunhui.cui@nxp.com>
Acked-by: NHan xu <han.xu@nxp.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().
Signed-off-by: NYunhui Cui <B56489@freescale.com>
Signed-off-by: NYunhui Cui <yunhui.cui@nxp.com>
Acked-by: NHan xu <han.xu@nxp.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Add GigaDevice GD25Q16 (16M-bit) to supported list.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

The page calculation under spi_nor_s3an_addr_convert() was wrong. On
Default Address Mode we need to perform a divide by page_size.
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

The first argument of ioread32_rep() and ioread8_rep is not
const. Change aspeed_smc_read_from_ahb() prototype to fix compile
warning :

   drivers/mtd/spi-nor/aspeed-smc.c: In function 'aspeed_smc_read_from_ahb':
   drivers/mtd/spi-nor/aspeed-smc.c:212:16: warning: passing argument 1 of 'ioread32_rep' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
      ioread32_rep(src, buf, len >> 2);
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This chip has write protection enabled on power-up,
so this flag is necessary to support write operations.
Signed-off-by: NVictor Shyba <victor1984@riseup.net>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This patch provides an alternative mean to support memory above 16MiB
(128Mib) by replacing 3byte address op codes by their associated 4byte
address versions.

Using the dedicated 4byte address op codes doesn't change the internal
state of the SPI NOR memory as opposed to using other means such as
updating a Base Address Register (BAR) and sending command to enter/leave
the 4byte mode.

Hence when a CPU reset occurs, early bootloaders don't need to be aware
of BAR value or 4byte mode being enabled: they can still access the first
16MiB of the SPI NOR memory using the regular 3byte address op codes.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Tested-by: NVignesh R <vigneshr@ti.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

This patch renames the SPINOR_OP_* macros of the 4-byte address
instruction set so the new names all share a common pattern: the 4-byte
address name is built from the 3-byte address name appending the "_4B"
suffix.

The patch also introduces new op codes to support other SPI protocols such
as SPI 1-4-4 and SPI 1-2-2.

This is a transitional patch and will help a later patch of spi-nor.c
to automate the translation from the 3-byte address op codes into their
4-byte address version.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NMark Brown <broonie@kernel.org>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

This driver adds mtd support for the Aspeed AST2400 SoC static memory
controllers:

 * New Static Memory Controller (referred as FMC)
   . BMC firmware
   . AST2500 compatible register set
   . 5 chip select pins (CE0 ∼ CE4)
   . supports NOR flash, NAND flash and SPI flash memory.

 * SPI Flash Controller (SPI)
   . host Firmware
   . slightly different register set, between AST2500 and the legacy
     controller
   . supports SPI flash memory
   . 1 chip select pin (CE0)

The legacy static memory controller (referred as SMC) is not
supported, as well as types other than SPI.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This driver adds mtd support for the Aspeed AST2500 SoC static memory
controllers :

 * Firmware SPI Memory Controller (FMC)
   . BMC firmware
   . 3 chip select pins (CE0 ~ CE2)
   . supports SPI type flash memory (CE0-CE1)
   . CE2 can be of NOR type flash but this is not supported by the
     driver

 * SPI Flash Controller (SPI1 and SPI2)
   . host firmware
   . 2 chip select pins (CE0 ~ CE1)
   . supports SPI type flash memory

Each controller has a memory range on which it maps its flash module
slaves. Each slave is assigned a memory window for its mapping that
can be changed at bootime with the Segment Address Register.

Each SPI flash slave can then be accessed in two modes: Command and
User. When in User mode, accesses to the memory segment of the slaves
are translated in SPI transfers. When in Command mode, the HW
generates the SPI commands automatically and the memory segment is
accessed as if doing a MMIO.

Currently, only the User mode is supported. Command mode needs a
little more work to check that the memory window on the AHB bus fits
the module size.

Based on previous work from Milton D. Miller II <miltonm@us.ibm.com>
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This patch removes the WARN_ONCE() test in spi_nor_write().
This macro triggers the display of a warning message almost every time we
use a UBI file-system because a write operation is performed at offset 64,
which is in the middle of the SPI NOR memory page. This is a valid
operation for ubifs.

Hence this warning is pretty annoying and useless so we just remove it.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Suggested-by: NRichard Weinberger <richard@nod.at>
Suggested-by: NAndras Szemzo <szemzo.andras@gmail.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The patch checks whether the Quad Enable bit is already set in the Status
Register. If so, the function exits immediately with a successful return
code.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep
their configuration data and (optionally) some user data.

The protocol of this flash follows most of the spi-nor standard. With
the following differences:

- Page size might not be a power of two.
- The address calculation (default addressing mode).
- The spi nor commands used.

Protocol is described on Xilinx User Guide UG333
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Trivial typo fix in comment.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The x86-64 and some other architectures are missing readsl/writesl
functions, so this driver won't build on them. Use a more portable
ioread32_rep()/iowrite32_rep() instead.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alan Tull <atull@opensource.altera.com>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Graham Moore <grmoore@opensource.altera.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Yves Vandervennet <yvanderv@opensource.altera.com>
Suggested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Add support for the SPI serial flash host controller found on many Intel
CPUs including Baytrail and Braswell. The SPI serial flash controller is
used to access BIOS and other platform specific information. By default the
driver exposes a single read-only MTD device but with a module parameter
"writeable=1" the MTD device can be made read-write which makes it possible
to upgrade BIOS directly from Linux.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

All fsl_qspi_devtype_data structures are never modified.
This patch constify them.
Signed-off-by: NLABBE Corentin <clabbe.montjoie@gmail.com>
Acked-by: NHan Xu <han.xu@nxp.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Add Everspin mr25h40 512KB MRAM to the list of supported chips.
Signed-off-by: NMasahiko Iwamoto <iwamoto@allied-telesis.co.jp>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Acked-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.

Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Jagan Teki <jteki@openedev.com>
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Add Atmel at25df321 spi-nor flash to the list of spi_nor_ids.

Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>
Acked-by: NWenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

We return success or possibly uninitialized values on these error paths
instead of proper error codes.

Fixes: 14062341 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

There are CQSPI_MAX_CHIPSELECT elements in the ->f_pdata array so the >
should be >=.

Fixes: 14062341 ('mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Signed-off-by: NSean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Acked-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

The Spansion S25FL128S also supports dual read mode.
In addition remove flag SECT_4K. 4K erases are supported,
but not uniformly.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>