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  1. 08 2月, 2021 3 次提交
  3. 05 2月, 2021 1 次提交
    • G
      drm/i915/display: Support PSR Multiple Instances · b64d6c51
      由 Gwan-gyeong Mun 提交于 
      It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR. And it not support multiple pipes with
a single transcoder PSR case yet.

v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
v5: Rebased and Addressed Anshuman's review comment.
    - Move calling of intel_psr_init() to intel_dp_init_connector()
v6: Address Anshuman's review comments
   - Remove wrong comments and add comments for a limit of supporting of
     a single pipe PSR
v7: Update intel_psr_compute_config() for supporting multiple transcoder
    PSR on BDW+
v8: Address Anshuman's review comments
   - Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
v9: Fix commit message
v10: Rebased
v11: Address Jose's review comment.
  - Reorder calling order of intel_psr2_program_trans_man_trk_ctl().
  - In order to reduce changes keep the old name for drm_i915_private.
  - Change restrictions of multiple instances of PSR.
v12: Address Jose's review comment.
  - Change the calling of intel_psr2_program_trans_man_trk_ctl() into
    commit_pipe_config().
  - Change a checking order of CAN_PSR() and connector_status to original
    on i915_psr_sink_status_show().
  - Drop unneeded intel_dp_update_pipe() function.
  - In order to wait a specific encoder which belong to crtc_state on
    intel_psr_wait_for_idle(), add checking of encoder.
  - Add an whitespace to comments.
v13: Rebased and Address Jose's review comment.
  - Add and use for_each_intel_psr_enabled_encoder() macro.
  - In order to use correct frontbuffer_bit for each pipe,
    fix intel_psr_invalidate() and intel_psr_flush().
  - Remove redundant or unneeded codes.
  - Update comments.
v14: Address Jose's review comment
  - Add and use for_each_intel_encoder_can_psr() macro and
    for_each_intel_encoder_mask_can_psr() macro.
  - Add source_support member variable into intel_psr structure.
  - Update CAN_PSR() macro that checks source_support.
  - Move encoder's PSR availity check to psr_init() from
    psr_compute_config().
  - Remove redundant or unneeded codes.
v15: Remove wrong mutex lock/unlock of PSR from
     intel_psr2_program_trans_man_trk_ctl()
Signed-off-by: NGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: NAnshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: NJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: NJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210204134015.419036-1-gwan-gyeong.mun@intel.com
      b64d6c51
  5. 21 1月, 2021 1 次提交
  7. 16 1月, 2021 1 次提交
  9. 14 1月, 2021 1 次提交
  11. 05 1月, 2021 1 次提交
  13. 22 12月, 2020 2 次提交
  15. 05 12月, 2020 1 次提交
  17. 19 11月, 2020 1 次提交
  19. 13 11月, 2020 1 次提交
  21. 12 11月, 2020 2 次提交
  23. 30 10月, 2020 3 次提交
  25. 21 10月, 2020 1 次提交
  27. 15 9月, 2020 1 次提交
  29. 11 9月, 2020 1 次提交
  31. 04 9月, 2020 2 次提交
  33. 07 7月, 2020 1 次提交
  35. 03 7月, 2020 1 次提交
  37. 01 7月, 2020 1 次提交
    • V
      drm/i915/fbc: Fix fence_y_offset handling · 5331889b
      由 Ville Syrjälä 提交于 
      The current fence_y_offset calculation is broken. I think it more or
less used to do the right thing, but then I changed the plane code
to put the final x/y source offsets back into the src rectangle so
now it's just subtraacting the same value from itself. The code would
never have worked if we allowed the framebuffer to have a non-zero
offset.

Let's do this in a better way by just calculating the fence_y_offset
from the final plane surface offset. Note that we don't align the
plane surface address to fence rows so with horizontal panning there's
often a horizontal offset from the fence start to the surface address
as well. We have no way to tell the hardware about that so we just
ignore it. Based on some quick tests the invlidation still happens
correctly. I presume due to the invalidation nuking at least the full
line (or a segment of multiple lines).

Fixes: 54d4d719 ("drm/i915: Overcome display engine stride limits via GTT remapping")
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200429101034.8208-4-ville.syrjala@linux.intel.comReviewed-by: NMatt Roper <matthew.d.roper@intel.com>
      5331889b
  39. 22 5月, 2020 1 次提交
  41. 24 4月, 2020 1 次提交
  43. 18 4月, 2020 1 次提交
  45. 04 4月, 2020 1 次提交
  47. 27 2月, 2020 1 次提交
  49. 26 2月, 2020 2 次提交
  51. 19 2月, 2020 1 次提交
  53. 31 1月, 2020 2 次提交
  55. 07 1月, 2020 1 次提交
  57. 29 12月, 2019 2 次提交
  59. 23 12月, 2019 1 次提交