1. 01 6月, 2019 1 次提交
  2. 30 4月, 2019 1 次提交
  3. 10 4月, 2019 2 次提交
  4. 11 12月, 2018 2 次提交
  5. 18 10月, 2018 4 次提交
  6. 05 9月, 2018 4 次提交
  7. 14 8月, 2018 1 次提交
  8. 24 7月, 2018 1 次提交
  9. 19 7月, 2018 1 次提交
  10. 02 6月, 2018 2 次提交
  11. 18 5月, 2018 1 次提交
  12. 27 3月, 2018 1 次提交
  13. 08 3月, 2018 1 次提交
    • A
      net/mlx5: Add flow-steering commands for FPGA IPSec implementation · 05564d0a
      Aviad Yehezkel 提交于
      In order to add a context to the FPGA, we need to get both the software
      transform context (which includes the keys, etc) and the
      source/destination IPs (which are included in the steering
      rule). Therefore, we register new set of firmware like commands for
      the FPGA. Each time a rule is added, the steering core infrastructure
      calls the FPGA command layer. If the rule is intended for the FPGA,
      it combines the IPs information with the software transformation
      context and creates the respective hardware transform.
      Afterwards, it calls the standard steering command layer.
      Signed-off-by: NAviad Yehezkel <aviadye@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      05564d0a
  14. 07 3月, 2018 2 次提交
  15. 29 12月, 2017 1 次提交
  16. 14 5月, 2017 1 次提交
  17. 17 4月, 2017 1 次提交
  18. 28 3月, 2017 2 次提交
  19. 10 11月, 2016 2 次提交
  20. 30 10月, 2016 1 次提交
    • M
      net/mlx5: Add multi dest support · 74491de9
      Mark Bloch 提交于
      Currently when calling mlx5_add_flow_rule we accept
      only one flow destination, this commit allows to pass
      multiple destinations.
      
      This change forces us to change the return structure to a more
      flexible one. We introduce a flow handle (struct mlx5_flow_handle),
      it holds internally the number for rules created and holds an array
      where each cell points the to a flow rule.
      
      From the consumers (of mlx5_add_flow_rule) point of view this
      change is only cosmetic and requires only to change the type
      of the returned value they store.
      
      From the core point of view, we now need to use a loop when
      allocating and deleting rules (e.g given to us a flow handler).
      Signed-off-by: NMark Bloch <markb@mellanox.com>
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leon@kernel.org>
      74491de9
  21. 18 8月, 2016 3 次提交
  22. 05 7月, 2016 2 次提交
  23. 03 7月, 2016 1 次提交
  24. 17 5月, 2016 2 次提交
    • A
      net/mlx5_core: Flow counters infrastructure · 43a335e0
      Amir Vadai 提交于
      If a counter has the aging flag set when created, it is added to a list
      of counters that will be queried periodically from a workqueue.  query
      result and last use timestamp are cached.
      add/del counter must be very efficient since thousands of such
      operations might be issued in a second.
      There is only a single reference to counters without aging, therefore
      no need for locks.
      But, counters with aging enabled are stored in a list. In order to make
      code as lockless as possible, all the list manipulation and access to
      hardware is done from a single context - the periodic counters query
      thread.
      
      The hardware supports multiple counters per FTE, however currently we
      are using one counter for each FTE.
      Signed-off-by: NAmir Vadai <amirva@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      43a335e0
    • A
      net/mlx5_core: Introduce flow steering destination of type counter · bd5251db
      Amir Vadai 提交于
      When adding a flow steering rule with a counter, need to supply a
      destination of type MLX5_FLOW_DESTINATION_TYPE_COUNTER, with a pointer
      to a struct mlx5_fc.
      Also, MLX5_FLOW_CONTEXT_ACTION_COUNT bit should be set in the action.
      Signed-off-by: NAmir Vadai <amirva@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bd5251db