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  1. 17 6月, 2012 2 次提交
    • A
      ARM: Kirkwood: Fix clk problems modular ethernet driver · 128789a8
      由 Andrew Lunn 提交于 
      When the ethernet driver was built as a module, it would lock the
machine when loaded. At boot the ethernet clks are unused, so get
turned off.  Later, when the module is loaded, the probe function
would access the hardware before the clock was restarted, and the
machine would lock. It has also been determined that when the clk is
turned off, the interface forgets its MAC address, which for most
systems, is set by the boot loader.

When the machine setup file creates a platform device for the
interface, prepare and enable the clock for the interface. This will
ensure it is not turned off. However, if the setup file only
instantiates one platform device, the other will have its clk
disabled, thus maybe saving a little power.
Report-by: NSimon Baatz <gmbnomis@gmail.com>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NSimon Baatz <gmbnomis@gmail.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>
      128789a8
    • A
      arm: versatile: fix and enable PCI I/O space · 9b0f7e39
      由 Arnd Bergmann 提交于 
      With commit 4d5fc58d (ARM: remove bunch of now unused
mach/io.h files), the I/O space setup was completely broken on
versatile. This patch fixes that and prepares for further
I/O space clean-up.

I/O space handling on the versatile platform is currently
broken in multiple ways. Most importantly, the ports do
not get mapped into the virtual address space at all.

Also, there is some amount of confusion between PCI I/O
space and other statically mapped MMIO registers in the
platform code:

* The __io_address() macro that is used to access the
  platform register maps to the same __io macro that gets
  used for I/O space.

* The IO_SPACE_LIMIT is set to a value that is much larger
  than the total available space.

* The I/O resource of the PCI bus is set to the physical
  address of the mapping, which is way outside of the
  actual I/O space limit as well as the address range that
  gets decoded by traditional PCI cards.

* No attempt is made to stay outside of the ISA port range
  that some device drivers try access.

* No resource gets requested as a child of ioport_resource,
  but an IORESOURCE_IO type mapping gets requested
  as a child of iomem_resource.

This patch attempts to correct all of the above. This makes
it possible to use virtio-pci based virtual devices as well
as actual PCI cards including those with legacy ISA port
ranges like VGA.

Some of the issues seem to be duplicated on other platforms.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
[rob: update to 3.5-rc2 and io.h cleanup related changes]
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Tested-by: NRobert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>
      9b0f7e39
  3. 08 6月, 2012 2 次提交
  5. 07 6月, 2012 3 次提交
  7. 06 6月, 2012 3 次提交
  9. 05 6月, 2012 4 次提交
  11. 04 6月, 2012 4 次提交
    • S
      ARM i.MX53: Fix PLL4 base address · cdd781ab
      由 Sascha Hauer 提交于 
      MX53_DPLL4_BASE accidently returned the base address of PLL3.
Fix this.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Cc: stable@vger.kernel.org
      cdd781ab
    • S
      ARM i.MX pllv2: make round_rate accurate · 9ca41bcc
      由 Sascha Hauer 提交于 
      in round_rate we made the assumption that we can set arbitrary
frequencies and thus returned the input rate. This is not correct,
for certain frequencies after setting a frequency with set_rate,
recalc_rate will return different values. To fix this, introduce
set_rate/recalc_rate functions which work on variables instead
of registers directly. This way we can call these in round_rate
to get the exact rate which we would get if we call set_rate
with this value.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      9ca41bcc
    • S
      ARM i.MX pllv2: use standard register set unconditionally · 6cc90d6d
      由 Sascha Hauer 提交于 
      The i.MX5 PLL has two different register sets for setting the
rate. One is used for the standard case and and is used for
DVFS. Which one of them is used depends on a hardware input
of the PLL. Current implementation reads back from the hardware
which setting is used. This is bogus: If we ever want to implement
DVFS we have to program both register sets and not only the one
which happens to be used at the moment. For now, just use the
standard register set uncondionally.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      6cc90d6d
    • T
      ARM: OMAP: Fix lis3lv02d accelerometer to use gpio_to_irq · 4d04317f
      由 Tony Lindgren 提交于 
      Commit 3b511201 (ARM: OMAP: rx51: Platform support for lis3lv02d accelerometer)
added support for lis3lv02d accelerometer.

The patch was still using OMAP_GPIO_IRQ which no longer exists.

Fix it by using gpio_to_irq().
Signed-off-by: NTony Lindgren <tony@atomide.com>
      4d04317f
  13. 02 6月, 2012 5 次提交
  15. 01 6月, 2012 15 次提交
  17. 31 5月, 2012 2 次提交