The BayTrail and CherryTrail platforms provide platform clocks
through their Power Management Controller (PMC).

The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a
frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail
and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks
are available for general system use, where appropriate, and each
have Control & Frequency register fields associated with them.

Port from legacy by Pierre Bossart, integration in clock framework
by Irina Tirdea
Signed-off-by: NIrina Tirdea <irina.tirdea@intel.com>
Signed-off-by: NPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK
was not explicit

Fixes: 701190fd ('clk: x86: add support for Lynxpoint LPSS clocks')
Signed-off-by: NPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In clock driver initialize phase the spinlock is missed to assignment
to struct clkgate_separated, finally there have no locking to protect
exclusive accessing for clock registers.

This bug introduces the console has no output after enable coresight
driver on 96boards Hikey; this is because console using UART3, which
has shared the same register with coresight clock enabling bit. After
applied this patch it can assign lock properly to protect exclusive
accessing, and console can work well after enabled coresight modules.

Fixes: 0aa0c95f ("clk: hisilicon: add common clock support")
Signed-off-by: NLeo Yan <leo.yan@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

These clocks have been broken for a long time unfortunately, a
hurdle of misc problems made them stop working at some point
breaking USB and audio on Ux500.

The platform as such and all "regular" clocks are migrated to
OF/device tree, so let's migrate also this driver.

With this patch and the corresponding DTS fixes, and a bunch
of probe deferral fixes, audio starts working again on Ux500.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The AB8500 sysclk is just another PRCMU-controlled clock, there
is no reason why it should be in the ABx500-controlled part of
the clock implementation. Doing this and the corresponding device
tree changes makes USB work on the Ux500 again.
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The MT8135 is a 32-bit SoC, so only propose it on ARM architecture,
not ARM64.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Fixes: 234d511d ("clk: mediatek: Add hardware dependency")
Cc: Andreas Färber <afaerber@suse.de>
Acked-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

If I say "no" to "Clock driver for Mediatek MT2701", I don't want to
be asked individually about each sub-driver. No means no.

Additionally, this driver shouldn't be proposed at all on non-mediatek
builds, unless build-testing.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Fixes: e9862118 ("clk: mediatek: Add MT2701 clock support")
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NJames Liao <jamesjj.liao@mediatek.com>
Cc: Shunli Wang <shunli.wang@mediatek.com>
Cc: Erin Lo <erin.lo@mediatek.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Currently the divider selection logic blindly divides the parent_rate
by the clk rate and gives the divider value for the divider clocks
which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider
table parsing to get the closest divider available in the table
provided via Device tree.

The code is pretty much taken from: drivers/clk/clk-divider.c.
and used here to fix up the best divider selection logic.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Reported-by: NRichard Woodruff <r-woodruff2@ti.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Once a gdsc is brought in and out of HW control, there is a
power down and up cycle which can take upto 1us. Polling on
the gdsc status immediately after the hw control enable/disable
can mislead software/firmware to belive the gdsc is already either on
or off, while its yet to complete the power cycle.
To avoid this add a 1us delay post a enable/disable of HW control
mode.

Also after the HW control mode is disabled, poll on the status to
check gdsc status reflects its 'on' before force disabling it
in software.
Reported-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Reviewed-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Tested-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Fixes: 904bb4f5 ("clk: qcom: gdsc: Add support for gdscs with HW control")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.

As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.

Fixed by just removing the second fixup.

Fixes: e31a1900 ("meson: clk: Add support for clock gates")
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch enables clocks for STM32F746 boards.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Do not let the entire probe function fail even if some clocks fail
to register.  Let's continue with succeeded clocks.  This will give
the system more chances to boot and allow us to investigate the
cause of the failure.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the OCOTP so that this hardware block can be used.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This proved incredibly useful during debugging of the DSI driver, to
see if our clocks were running at rate we requested.  Let's leave it
here for the next person interacting with clocks on the platform (and
so that hopefully we can just hook it up to debugfs some day).
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The DSI pixel clocks are muxed from clocks generated in the analog phy
by the DSI driver.  In order to set them as parents, we need to do the
same name lookup dance on them as we do for our root oscillator.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Our core PLLs are intended to be configured once and left alone.  With
the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
change PLLD just to get closer to the requested DSI clock, thus
changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
it, and breaking ethernet.

We *do* want PLLH to change so that PLLH_AUX can be exactly the value
we want, though.  Thus, we need to have a per-divider policy of
whether to pass rate changes up.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

CS2000 needs re-setup when redume, otherwise, it can't
handle correct clock rate.
Signed-off-by: NKhiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
[Kuninori: cleanup original patch]
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
chips have two clock inputs, XTAL or CLK, which are muxed into single
PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip
while the 5P49V5923 requires external XTAL.

The PLL feeds two fractional dividers. Each fractional divider feeds
output mux, which allows selecting between clock from the fractional
divider itself or from output mux on output N-1. In case of output
mux 0, the output N-1 is instead connected to the output from the mux
feeding the PLL.

The driver thus far supports only the 5P49V5923 and 5P49V5933, while
it should be easily extensible to the whole 5P49V59xx family of chips
as they are all pretty similar.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The LDB mux/gate layout has been fixed on QuadPlus, so there is no need
to restrict the LDB mux changes on this hardware, as the erratum
preventing this from working properly is gone.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Support for Exynos4415 is going away because there are no internal nor
external users.

Since commit 46dcf0ff ("ARM: dts: exynos: Remove exynos4415.dtsi"),
the platform cannot be instantiated so remove also the drivers.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NKukjin Kim <kgene@kernel.org>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Add the newly added clock ids to the clock entries of the rk3066/rk3188
clock driver. We won't be needing them in the kernel for a bit yet
but as they're used in the new u-boot ddr setup code/dts we should make
sure the clock ids stay identical and do not differ.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Reference the newly added isp clock-ids in the clock-tree.
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The failure path in the newly added function tries to free an
uninitialized pointer:

drivers/clk/clk-stm32f4.c: In function 'stm32f4_rcc_init':
drivers/clk/clk-stm32f4.c:1106:4: error: 'gate' may be used uninitialized in this function [-Werror=maybe-uninitialized]

I'm adding an initialization to NULL here to make the kfree()
succeed, and I'm also rearranging the cleanup so that the
same kfree() is used for any error path, making the function
slightly more robust against newly introduced bugs in the
error handling.

Fixes: daf2d117 ("clk: stm32f4: Add lcd-tft clock")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The CDCE925 is a member of the CDCE(L)9xx programmable clock generator
family.  There are also CDCE913, CDCE937, CDCE949 which have different
number of PLLs and outputs.

The clk-cdce925 driver supports only CDCE925 in the family.  This adds
support for the CDCE913, CDCE937, CDCE949, too.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Cc: Michael Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add definition of EBI2 clock used by MDM9615 NAND controller.

Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: NZoran Markovic <zmarkovic@sierrawireless.com>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This include was needed to suppress build error when this driver
was initially merged because <linux/regmap.h> did not include
<linux/delay.h> at that time.  (developers' headache across
sub-systems)

The root cause has been fixed by commit adf08d48 ("regmap:
include <linux/delay.h> from include/linux/regmap.h"), so this
line can be dropped now.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This commit adjusts the list of possible "Sample At Reset" values that
define the CPU clock frequency of the AP806 (part of Marvell Armada
7K/8K) to the values that have been validated with the production
chip. Earlier values were preliminary.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add clock drivers for hi3660 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
[sboyd@codeaurora.org: Simplify probe with function pointer]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some parent clocks of the Exynos542x clock blocks, which have separate
power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always
enabled to access any register related to power management unit or devices
connected to it. For the time being, until a proper solution based on
runtime PM is applied, mark those clocks as critical (instead of ignore
unused or even no flags) to prevent disabling them.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

EPROBE_DEFER is not an error, hence printing an error message like

	clk: couldn't get clock 0 for /soc/display@feb00000

may confuse the user.

Suppress error messages in case of probe deferral to fix this.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Currently we add the virtual cpufreq device unconditionally even when
the SCPI DVFS clock provider node is disabled. This will cause cpufreq
driver to throw errors when it gets initailised on boot/modprobe and
also when the CPUs are hot-plugged back in.

This patch fixes the issue by adding the virtual cpufreq device only if
the SCPI DVFS clock provider is available and registered.

Fixes: 9490f01e ("clk: scpi: add support for cpufreq virtual device")
Reported-by: NMichał Zegan <webczat_200@poczta.onet.pl>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Tested-by: NMichał Zegan <webczat_200@poczta.onet.pl>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support to use reset control framework for resetting MSS
with hexagon v56 1.5.0.
Signed-off-by: NAvaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The audio related clock support is missing from the existing zx296718
clock driver.  Let's add it, so that the upstream ZX SPDIF driver can
work for HDMI audio support.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
[sboyd@codeaurora.org: Staticize some more structures]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Instead of using panic, we should give an error message and return error
code when of_clk_add_hw_provider() call fails.

Since we have error prompt for failures, the "init over" pr_info output
isn't really necessary but becomes a debug noise.  So let's clean it up
along the way.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The delay here is not in atomic context and does not seem critical with
respect to precision, but usleep_range(min,max) with min==max results in
giving the timer subsystem no room to optimize uncritical delays. Fix
this by setting the range to 2000,3000 us.

Fixes: commit f05259a6 ("clk: wm831x: Add initial WM831x clock driver")
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Acked-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

On vf610, PLL1 and PLL2 have registers to configure fractional part of
frequency multiplier.

This patch adds support for these registers.

This fixes "fast system clock" issue on boards where bootloader sets
fractional multiplier for PLL1.
Suggested-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
CC: Chris Healy <cphealy@gmail.com>
Signed-off-by: NNikita Yushchenko <nikita.yoush@cogentembedded.com>
Tested-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Init field must be cleared in driver probe as this structure is not
dinamically allocated. If not, wrong flags can be passed to core.
Signed-off-by: NJose Abreu <joabreu@synopsys.com>
Cc: Carlos Palminha <palminha@synopsys.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Fixes: 923587aa ("clk/axs10x: Add I2S PLL clock driver")
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com

When we used to defer setting the "grf" member to
rockchip_clk_get_grf() it was important to init the "grf" member to an
error value in rockchip_clk_init().  With recent changes, we now set
"grf" right in rockchip_clk_init() (two lines below the place where we
initted it).  That makes the old init useless.  Get rid of it.

Fixes: 6f339dc2 ("clk: rockchip: lookup General Register Files in rockchip_clk_init")
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add the clock tree definition for the new rk3328 SoC.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The rk3328's pll and clock are similar with rk3036's,
it different with pll_mode_mask, the rk3328 soc
pll mode only one bit(rk3036 soc have two bits)
so these should be independent and separate from
the series of rk3328s.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>