1. 05 1月, 2018 1 次提交
  2. 22 12月, 2017 2 次提交
    • A
      ARM: dts: tango4: remove bogus interrupt-controller property · fbd90b4c
      Arnd Bergmann 提交于
      dtc points out that the parent node of the interrupt controllers is not
      actually an interrupt controller itself, and lacks an #interrupt-cells
      property:
      
      arch/arm/boot/dts/tango4-vantage-1172.dtb: Warning (interrupts_property): Missing #interrupt-cells in interrupt-parent /soc/interrupt-controller@6e000
      
      This removes the annotation.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      fbd90b4c
    • A
      ARM: dts: ls1021a: fix incorrect clock references · 506e8a91
      Arnd Bergmann 提交于
      dtc warns about two 'clocks' properties that have an extraneous '1'
      at the end:
      
      arch/arm/boot/dts/ls1021a-qds.dtb: Warning (clocks_property): arch/arm/boot/dts/ls1021a-twr.dtb: Warning (clocks_property): Property 'clocks', cell 1 is not a phandle reference in /soc/i2c@2180000/mux@77/i2c@4/sgtl5000@2a
      arch/arm/boot/dts/ls1021a-qds.dtb: Warning (clocks_property): Missing property '#clock-cells' in node /soc/interrupt-controller@1400000 or bad phandle (referred from /soc/i2c@2180000/mux@77/i2c@4/sgtl5000@2a:clocks[1])
      Property 'clocks', cell 1 is not a phandle reference in /soc/i2c@2190000/sgtl5000@a
      arch/arm/boot/dts/ls1021a-twr.dtb: Warning (clocks_property): Missing property '#clock-cells' in node /soc/interrupt-controller@1400000 or bad phandle (referred from /soc/i2c@2190000/sgtl5000@a:clocks[1])
      
      The clocks that get referenced here are fixed-rate, so they do not
      take any argument, and dtc interprets the next cell as a phandle, which
      is invalid.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      506e8a91
  3. 21 12月, 2017 2 次提交
  4. 19 12月, 2017 1 次提交
  5. 18 12月, 2017 1 次提交
  6. 14 12月, 2017 1 次提交
  7. 08 12月, 2017 1 次提交
  8. 07 12月, 2017 5 次提交
  9. 06 12月, 2017 2 次提交
  10. 05 12月, 2017 3 次提交
  11. 04 12月, 2017 1 次提交
  12. 03 12月, 2017 2 次提交
  13. 01 12月, 2017 3 次提交
  14. 30 11月, 2017 1 次提交
  15. 29 11月, 2017 7 次提交
  16. 28 11月, 2017 7 次提交
    • A
      ARM: dts: logicpd-som-lv: Fix gpmc addresses for NAND and enet · 3c18bbf3
      Adam Ford 提交于
      This patch fixes and issue where the NAND and GPMC based ethernet
      controller stopped working.  This also updates the GPMC settings
      to be consistent with the Logic PD Torpedo development from the
      commit listed above.
      
      Fixes: 44e47164 ("ARM: dts: omap3: Fix NAND device nodes")
      Signed-off-by: NAdam Ford <aford173@gmail.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      3c18bbf3
    • T
      ARM: dts: Fix omap4 hang with GPS connected to USB by using wakeupgen · cf87634c
      Tony Lindgren 提交于
      There's been a reproducable USB OHCI/EHCI cpuidle related hang on omap4
      for a while that happens after about 20 - 40 minutes on an idle system
      with some data feeding device being connected, like a USB GPS device or
      a cellular modem.
      
      This issue happens in cpuidle states C2 and C3 and does not happen if
      cpuidle is limited to C1 state only. The symptoms are that the whole
      system hangs and never wakes up from idle, and if a watchdog is
      configured the system reboots after a while.
      
      Turns out that OHCI/EHCI devices on omap4 are trying to use the GIC
      interrupt controller directly as a parent instead of the WUGEN. We
      need to pass the interrupts through WUGEN to GIC to provide the wakeup
      events for the processor.
      
      Let's fix the issue by removing the gic interrupt-parent and use the
      default interrupt-parent wakeupgen instead. Note that omap5.dtsi had
      this already fixes earlier by commit 7136d457 ("ARM: omap: convert
      wakeupgen to stacked domains") but we somehow missed omap4 at that
      point.
      
      Fixes: 7136d457 ("ARM: omap: convert wakeupgen to stacked domains")
      Cc: Dave Gerlach <d-gerlach@ti.com>
      Cc: Nishanth Menon <nm@ti.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
      Reviewed-by: NRoger Quadros <rogerq@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      cf87634c
    • D
      ARM: OMAP2+: Missing error code in omap_device_build() · e9a9bb4e
      Dan Carpenter 提交于
      We need to set the error code if omap_device_alloc() fails.
      Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      e9a9bb4e
    • K
      ARM: AM33xx: PRM: Remove am33xx_pwrdm_read_prev_pwrst function · b6d6af72
      Keerthy 提交于
      Referring TRM Am335X series:
      http://www.ti.com/lit/ug/spruh73p/spruh73p.pdf
      
      The LastPowerStateEntered bitfield is present only for PM_CEFUSE
      domain. This is not present in any of the other power domains. Hence
      remove the generic am33xx_pwrdm_read_prev_pwrst hook which wrongly
      reads the reserved bit fields for all the other power domains.
      
      Reading the reserved bits leads to wrongly interpreting the low
      power transitions for various power domains that do not have the
      LastPowerStateEntered field. The pm debug counters values are wrong
      currently as we are incrementing them based on the reserved bits.
      Signed-off-by: NKeerthy <j-keerthy@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      b6d6af72
    • T
      ARM: OMAP2+: Fix SRAM virt to phys translation for save_secure_ram_context · d09220a8
      Tony Lindgren 提交于
      With the CMA changes from Joonsoo Kim <iamjoonsoo.kim@lge.com>, it
      was noticed that n900 stopped booting. After investigating it turned
      out that n900 save_secure_ram_context does some whacky virtual to
      physical address translation for the SRAM data address.
      
      As we now only have minimal parts of omap3 idle code copied to SRAM,
      running save_secure_ram_context() in SRAM is not needed. It only gets
      called on PM init. And it seems there's no need to ever call this from
      SRAM idle code.
      
      So let's just keep save_secure_ram_context() in DDR, and pass it the
      physical address of the parameters. We can do everything else in
      omap-secure.c like we already do for other secure code.
      
      And since we don't have any documentation, I still have no clue what
      the values for 0, 1 and 1 for the parameters might be. If somebody has
      figured it out, please do send a patch to add some comments.
      Debugged-by: NJoonsoo Kim <iamjoonsoo.kim@lge.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      d09220a8
    • F
      ARM: dts: NSP: Fix PPI interrupt types · 5f1aa51c
      Florian Fainelli 提交于
      Booting a kernel results in the kernel warning us about the following
      PPI interrupts configuration:
      [    0.105127] smp: Bringing up secondary CPUs ...
      [    0.110545] GIC: PPI11 is secure or misconfigured
      [    0.110551] GIC: PPI13 is secure or misconfigured
      
      Fix this by using the appropriate edge configuration for PPI11 and
      PPI13, this is similar to what was fixed for Northstar (BCM5301X) in
      commit 0e34079c ("ARM: dts: BCM5301X: Correct GIC_PPI interrupt
      flags").
      
      Fixes: 7b2e987d ("ARM: NSP: add minimal Northstar Plus device tree")
      Fixes: 1a9d53ca ("ARM: dts: NSP: Add TWD Support to DT")
      Acked-by: NJon Mason <jon.mason@broadcom.com>
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      5f1aa51c
    • F
      ARM: dts: NSP: Disable AHCI controller for HR NSP boards · 77416ab3
      Florian Fainelli 提交于
      The AHCI controller is currently enabled for all of these boards:
      bcm958623hr and bcm958625hr would result in a hard hang on boot that we
      cannot get rid of. Since this does not appear to have an easy and simple
      fix, just disable the AHCI controller for now until this gets resolved.
      
      Fixes: 70725d6e ("ARM: dts: NSP: Enable SATA on bcm958625hr")
      Fixes: d454c376 ("ARM: dts: NSP: Add new DT file for bcm958623hr")
      Acked-by: NJon Mason <jon.mason@broadcom.com>
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      77416ab3