Doing this in combination with "atmel_spi: fix hang due to missed
interrupt" appears to eliminate the overruns I'm seeing when using
JFFS2-on-DataFlash as /usr filesystem on the ATNGW100.
Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>

Update all avr32-specific files to use the new platform-specific header
locations. Drivers shared with ARM are left alone for now.
Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>

This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.

This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.

This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)

Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.

The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.

The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.

Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:

http://www.atmel.com/dyn/products/datasheets.asp?family_id=682Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>

Basic I2C initialization for the NGW100 board:

  - Provide empty i2c device table. Daughtercards may add devices,
    and the ATtiny24 could do stuff too.

  - Set up EXTINT(3) so the ATtiny24 can interrupt the AP7000.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>

On our custom board we have other oscillator rates than on atngw100 and
atstk100x.

Currently these rates are hardcoded in arch/avr32/mach-at32ap/at32ap700x.c.

This patch moves them into board specific code.
Signed-off-by: NAlex Raimondi <raimondi@miromico.ch>
Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>

These are derivatives of the AT32AP7000 chip, which means that most of
the code stays the same. Rename a few files, functions, definitions
and config symbols to reflect that they apply to all AP700x chips, and
exclude some platform devices from chips where they aren't present.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Make the NGW100 bitbang i2c use open drain signaling.

Also, speed it up, so it's closer to 100 kHz ... the code paths seem
to be long enough that the udelay isn't dominating bit times.  The
peak bit rate I observed was around 125 kHz, but that's with large
delays (usually before ACK/NAK) which hold the overall rate down to
around 80 kHz (call it 100 usec/byte on average).
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Implement at32_add_device_usba() and use it to wire up the USBA device
on ATSTK1000 and ATNGW100.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

The NGW100 has a board controller which is hooked up to the TWI lines
on AP7000. Since the TWI driver isn't in mainline, use the i2c-gpio
driver in the mean time.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Add GPIO leds to the NGW100 platform and its defconfig.
Access through /sys/class/leds/{a,b,sys}/* files; one
defaults to a heartbeat.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NRichard Purdie <rpurdie@rpsys.net>

USART mapping used to be accomplished by the manual filling of
at32_usart_map[] and at32_nr_usarts.  This has now been replaced
with at32_map_usart() so we can remove these variables.
Signed-off-by: NBen Nizette <ben.nizette@iinet.net.au>
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Add board code and defconfig for the ATNGW100 Network Gateway kit.
For more information about this board, see

http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4102Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Since the core setup code takes care of both allocation and
reservation of framebuffer memory, there's no need for this board-
specific hook anymore. Replace it with two global variables,
fbmem_start and fbmem_size, which can be used directly.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Set up one spi_board_info array per controller and pass this to
at32_add_device_spi so that it can set up any GPIO pins for chip
selects based on this information.

Extracted from a patch by David Brownell and adapted slightly.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Move stuff in spi.c into ATSTK1002 board code and update SPI
platform device definitions according to the new GPIO API.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

The PIOE device was left out before because it muxes SDRAM pins (and
is therefore a bit dangerous to mess with) and because no existing
drivers had any use for it.

It is needed for CompactFlash, however, and now that we have a way
to protect the SDRAM pins, it can be safely added.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Fixes to USART setup on the stk-1000 ... don't configure USART 2, since
its TXD/RXD are used for INT-A and INT-B buttons; and configure USART 0
(for IRDA, and with corrected IRQ) iff SW2 has a non-default setting.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

The macb driver will probe for the PHY chip and read the mac address
from the MACB registers, so we don't need them in eth_platform_data
anymore.

Since u-boot doesn't currently initialize the MACB registers with the
mac addresses, the tag parsing code is kept but instead of sticking
the information into eth_platform_data, it uses it to initialize
the MACB registers (in case the boot loader didn't do it.) This code
should be unnecessary at some point in the future.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

By moving the ethernet tag parsing to the board-specific code we avoid
the issue of figuring out which device we're supposed to attach the
information to.  The board specific code knows this because it's
where the actual devices are instantiated.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Allow the board to remap actual USART peripheral devices to serial
devices by calling at32_map_usart(hw_id, serial_line). This ensures
that even though ATSTK1002 uses USART1 as the first serial port, it
will still have a ttyS0 device.

This also adds a board-specific early setup hook and moves the
at32_setup_serial_console() call there from the platform code.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.

AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density.  The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.

The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf

The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture.  It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit.  It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.

Full data sheet is available from

http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf

while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf

Information about the AT32STK1000 development board can be found at

http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918

including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.

Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.

This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.

[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NDave McCracken <dmccr@us.ibm.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>