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  1. 04 9月, 2017 10 次提交
  3. 30 8月, 2017 6 次提交
    • P
      clocksource: mips-gic-timer: Use new GIC accessor functions · e07127a0
      由 Paul Burton 提交于 
      Switch from calling functions exported by the GIC interrupt controller
to using new accessors provided by asm/mips-gic.h. This will allow the
counter-handling functionality to be removed from the interrupt
controller driver, where it doesn't really belong, and also allow for
inlining of the accesses to the GIC.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17021/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e07127a0
    • P
      MIPS: GIC: Introduce asm/mips-gic.h with accessor functions · 582e2b4a
      由 Paul Burton 提交于 
      This patch introduces a new header providing accessor functions for the
MIPS Global Interrupt Controller (GIC) mirroring those provided for the
other 2 components of the MIPS Coherent Processing System (CPS) - the
Coherence Manager (CM) & Cluster Power Controller (CPC).

This header makes use of the new standardised CPS accessor macros where
possible, but does require some custom accessors for cases where we have
either a bit or a register per interrupt.

A major advantage of this over the existing
include/linux/irqchip/mips-gic.h definitions is that code performing
accesses can become much simpler, for example this:

  gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
                  GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
                  (unsigned long)trig << GIC_INTR_BIT(intr));

...can become simply:

  change_gic_trig(intr, trig);

The accessors handle 32 vs 64 bit in the same way as for CM & CPC code,
which means that GIC code will also not need to worry about the access
size in most cases. They are also accessible outside of
drivers/irqchip/irq-mips-gic.c which will allow for simplification in
the use of the non-interrupt portions of the GIC (eg. counters) which
currently require the interrupt controller driver to expose helper
functions for access.

This patch doesn't change any existing code over to use the new
accessors yet, since a wholesale change would be invasive & difficult to
review. Instead follow-on patches will convert code piecemeal to use
this new header. The one change to existing code is to rename gic_base
to mips_gic_base & make it global, in order to fit in with the naming
expected by the standardised CPS accessor macros.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17020/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      582e2b4a
    • J
      irqchip: mips-gic: SYNC after enabling GIC region · a0ffec3d
      由 James Hogan 提交于 
      A SYNC is required between enabling the GIC region and actually trying
to use it, even if the first access is a read, otherwise its possible
depending on the timing (and in my case depending on the precise
alignment of certain kernel code) to hit CM bus errors on that first
access.

Add the SYNC straight after setting the GIC base.

[paul.burton@imgtec.com:
  Changes later in this series increase our likelihood of hitting this
  by reducing the amount of code that runs between enabling the GIC &
  accessing it.]

Fixes: a7057270 ("irqchip: mips-gic: Add device-tree support")
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17019/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a0ffec3d
    • P
      MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers · e83f7e02
      由 Paul Burton 提交于 
      With Coherence Manager (CM) 3.5 information about the topology of the
system, which has previously only been available through & accessed from
the CM, is now also provided by the Cluster Power Controller (CPC). This
includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a
new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG.

In preparation for adjusting functions such as mips_cm_numcores(), which
have previously only needed to access the CM, to also access the CPC
this patch modifies the way we use the various CPS headers. Rather than
having users include asm/mips-cm.h or asm/mips-cpc.h individually we
instead have users include asm/mips-cps.h which in turn includes
asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access
to both CM & CPC registers by including one header, and most importantly
it makes asm/mips-cps.h an ideal location for helper functions which
need to access the various components of the CPS.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17015/
Patchwork: https://patchwork.linux-mips.org/patch/17217/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e83f7e02
    • P
      MIPS: Unify checks for sibling CPUs · fe7a38c6
      由 Paul Burton 提交于 
      Up until now we have open-coded checks for whether CPUs are siblings,
with slight variations on whether we consider the package ID or not.

This will only get more complex when we introduce cluster support, so in
preparation for that this patch introduces a cpus_are_siblings()
function which can be used to check whether or not 2 CPUs are siblings
in a consistent manner.

By checking globalnumber with the VP ID masked out this also has the
neat side effect of being ready for multi-cluster systems already.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NRafael J. Wysocki <rjw@rjwysocki.net>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17011/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      fe7a38c6
    • P
      MIPS: Abstract CPU core & VP(E) ID access through accessor functions · f875a832
      由 Paul Burton 提交于 
      We currently have fields in struct cpuinfo_mips for the core & VP(E) ID
of a particular CPU, and various pieces of code directly access those
fields. This patch abstracts such access by introducing accessor
functions cpu_core(), cpu_set_core(), cpu_vpe_id() & cpu_set_vpe_id()
and having code that needs to access these values call those functions
rather than directly accessing the struct cpuinfo_mips fields. This
prepares us for changes to the way in which those values are stored in
later patches.

The cpu_vpe_id() function is introduced even though we already had a
cpu_vpe_id() macro for a couple of reasons:

  1) It's more consistent with the core, and future cluster, accessors.

  2) It ensures a sensible return type without explicit casts.

  3) It's generally preferable to use functions rather than macros.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17009/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      f875a832
  5. 29 8月, 2017 2 次提交
    • P
      MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts · 93c5bba5
      由 Paul Burton 提交于 
      There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h
when declaring macros corresponding to register fields. This patch
modifies our definitions to do so.

The *_SHF definitions are removed entirely - they duplicate information
found in the masks, are infrequently used & can be replaced with use of
__ffs() where needed.

The *_MSK definitions then lose their _MSK suffix which is now somewhat
redundant, and users are modified to match.

The field definitions are moved to follow the appropriate register's
accessor functions, which helps to keep the field definitions in order &
to find the appropriate fields for a given register. Whilst here a
comment is added describing each register & including its name, which is
helpful both for linking the register back to hardware documentation &
for grepping purposes.

This also cleans up a couple of issues that became obvious as a result
of making the changes described above:

  - We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony
    copy of that named GCR_RESET_EXT_BASE - a register which does not
    exist. The bad definitions were added by commit 497e803e ("MIPS:
    smp-cps: Ensure secondary cores start with EVA disabled") and made
    use of from boot_core(), which is now modified to use the
    GCR_Cx_RESET_EXT_BASE definitions.

  - We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly
    define this as inFo rather than inGo.

Now that we don't duplicate field information between _SHF & _MSK
definitions, and keep the fields next to the register accessors, it will
be much easier to spot & prevent any similar oddities being introduced
in the future.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17001/
Patchwork: https://patchwork.linux-mips.org/patch/17216/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      93c5bba5
    • M
      MIPS: Alchemy: Threaded carddetect irqs for devboards · cc10815e
      由 Manuel Lauss 提交于 
      This introduces threaded carddetect irqs for the db1200/db1300 boards.
Main benefit is that the broken insertion/ejection interrupt pairs
can now be better supported and debounced in software.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15287/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      cc10815e
  7. 26 8月, 2017 3 次提交
  9. 25 8月, 2017 7 次提交
    • B
      mtd: nand: atmel: Relax tADL_min constraint · be3e83e3
      由 Boris Brezillon 提交于 
      Version 4 of the ONFI spec mandates that tADL be at least 400 nanoseconds,
but, depending on the master clock rate, 400 ns may not fit in the tADL
field of the SMC reg. We need to relax the check and accept the -ERANGE
return code.

Note that previous versions of the ONFI spec had a lower tADL_min (100 or
200 ns). It's not clear why this timing constraint got increased but it
seems most NANDs are fine with values lower than 400ns, so we should be
safe.

Fixes: f9ce2edd ("mtd: nand: atmel: Add ->setup_data_interface() hooks")
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      be3e83e3
    • U
      mtd: nandsim: remove debugfs entries in error path · b974696d
      由 Uwe Kleine-König 提交于 
      The debugfs entries must be removed before an error is returned in the
probe function. Otherwise another try to load the module fails and when
the debugfs files are accessed without the module loaded, the kernel
still tries to call a function in that module.

Fixes: 5346c27c ("mtd: nandsim: Introduce debugfs infrastructure")
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: NRichard Weinberger <richard@nod.at>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      b974696d
    • M
      Input: ALPS - fix two-finger scroll breakage in right side on ALPS touchpad · 4a646580
      由 Masaki Ota 提交于 
      Fixed the issue that two finger scroll does not work correctly
on V8 protocol. The cause is that V8 protocol X-coordinate decode
is wrong at SS4 PLUS device. I added SS4 PLUS X decode definition.

Mote notes:
the problem manifests itself by the commit e7348396 ("Input: ALPS
- fix V8+ protocol handling (73 03 28)"), where a fix for the V8+
protocol was applied.  Although the culprit must have been present
beforehand, the two-finger scroll worked casually even with the
wrongly reported values by some reason.  It got broken by the commit
above just because it changed x_max value, and this made libinput
correctly figuring the MT events.  Since the X coord is reported as
falsely doubled, the events on the right-half side go outside the
boundary, thus they are no longer handled.  This resulted as a broken
two-finger scroll.

One finger event is decoded differently, and it didn't suffer from
this problem.  The problem was only about MT events. --tiwai

Fixes: e7348396 ("Input: ALPS - fix V8+ protocol handling (73 03 28)")
Signed-off-by: NMasaki Ota <masaki.ota@jp.alps.com>
Tested-by: NTakashi Iwai <tiwai@suse.de>
Tested-by: NPaul Donohue <linux-kernel@PaulSD.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: NTakashi Iwai <tiwai@suse.de>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
      4a646580
    • E
      pty: Repair TIOCGPTPEER · 311fc65c
      由 Eric W. Biederman 提交于 
      The implementation of TIOCGPTPEER has two issues.

When /dev/ptmx (as opposed to /dev/pts/ptmx) is opened the wrong
vfsmount is passed to dentry_open.  Which results in the kernel displaying
the wrong pathname for the peer.

The second is simply by caching the vfsmount and dentry of the peer it leaves
them open, in a way they were not previously Which because of the inreased
reference counts can cause unnecessary behaviour differences resulting in
regressions.

To fix these move the ioctl into tty_io.c at a generic level allowing
the ioctl to have access to the struct file on which the ioctl is
being called.  This allows the path of the slave to be derived when
opening the slave through TIOCGPTPEER instead of requiring the path to
the slave be cached.  Thus removing the need for caching the path.

A new function devpts_ptmx_path is factored out of devpts_acquire and
used to implement a function devpts_mntget.   The new function devpts_mntget
takes a filp to perform the lookup on and fsi so that it can confirm
that the superblock that is found by devpts_ptmx_path is the proper superblock.

v2: Lots of fixes to make the code actually work
v3: Suggestions by Linus
    - Removed the unnecessary initialization of filp in ptm_open_peer
    - Simplified devpts_ptmx_path as gotos are no longer required

[ This is the fix for the issue that was reverted in commit
  143c97cc, but this time without breaking 'pbuilder' due to
  increased reference counts   - Linus ]

Fixes: 54ebbfb1 ("tty: add TIOCGPTPEER ioctl")
Reported-by: NChristian Brauner <christian.brauner@canonical.com>
Reported-and-tested-by: NStefan Lippers-Hollmann <s.l-h@gmx.de>
Signed-off-by: N"Eric W. Biederman" <ebiederm@xmission.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      311fc65c
    • M
      IB/mlx5: Always return success for RoCE modify port · ec255879
      由 Majd Dibbiny 提交于 
      CM layer calls ib_modify_port() regardless of the link layer.

For the Ethernet ports, qkey violation and Port capabilities
are meaningless. Therefore, always return success for ib_modify_port
calls on the Ethernet ports.

Cc: Selvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: NMajd Dibbiny <majd@mellanox.com>
Reviewed-by: NMoni Shoua <monis@mellanox.com>
Signed-off-by: NLeon Romanovsky <leon@kernel.org>
Signed-off-by: NDoug Ledford <dledford@redhat.com>
      ec255879
    • M
      IB/mlx5: Fix Raw Packet QP event handler assignment · 1d31e9c0
      由 Majd Dibbiny 提交于 
      In case we have SQ and RQ for Raw Packet QP, the SQ's event handler
wasn't assigned.

Fixing this by assigning event handler for each WQ after creation.

[ 1877.145243] Call Trace:
[ 1877.148644] <IRQ>
[ 1877.150580] [<ffffffffa07987c5>] ? mlx5_rsc_event+0x105/0x210 [mlx5_core]
[ 1877.159581] [<ffffffffa0795bd7>] ? mlx5_cq_event+0x57/0xd0 [mlx5_core]
[ 1877.167137] [<ffffffffa079208e>] mlx5_eq_int+0x53e/0x6c0 [mlx5_core]
[ 1877.174526] [<ffffffff8101a679>] ? sched_clock+0x9/0x10
[ 1877.180753] [<ffffffff810f717e>] handle_irq_event_percpu+0x3e/0x1e0
[ 1877.188014] [<ffffffff810f735d>] handle_irq_event+0x3d/0x60
[ 1877.194567] [<ffffffff810f9fe7>] handle_edge_irq+0x77/0x130
[ 1877.201129] [<ffffffff81014c3f>] handle_irq+0xbf/0x150
[ 1877.207244] [<ffffffff815ed78a>] ? atomic_notifier_call_chain+0x1a/0x20
[ 1877.214829] [<ffffffff815f434f>] do_IRQ+0x4f/0xf0
[ 1877.220498] [<ffffffff815e94ad>] common_interrupt+0x6d/0x6d
[ 1877.227025] <EOI>
[ 1877.228967] [<ffffffff814834e2>] ? cpuidle_enter_state+0x52/0xc0
[ 1877.236990] [<ffffffff81483615>] cpuidle_idle_call+0xc5/0x200
[ 1877.243676] [<ffffffff8101bc7e>] arch_cpu_idle+0xe/0x30
[ 1877.249831] [<ffffffff810b4725>] cpu_startup_entry+0xf5/0x290
[ 1877.256513] [<ffffffff815cfee1>] start_secondary+0x265/0x27b
[ 1877.263111] Code: Bad RIP value.
[ 1877.267296] RIP [< (null)>] (null)
[ 1877.273264] RSP <ffff88046fd63df8>
[ 1877.277531] CR2: 0000000000000000

Fixes: 19098df2 ("IB/mlx5: Refactor mlx5_ib_qp to accommodate other QP types")
Signed-off-by: NMajd Dibbiny <majd@mellanox.com>
Reviewed-by: NYishai Hadas <yishaih@mellanox.com>
Signed-off-by: NLeon Romanovsky <leon@kernel.org>
Signed-off-by: NDoug Ledford <dledford@redhat.com>
      1d31e9c0
    • N
      IB/core: Avoid accessing non-allocated memory when inferring port type · 498ca3c8
      由 Noa Osherovich 提交于 
      Commit 44c58487 ("IB/core: Define 'ib' and 'roce' rdma_ah_attr types")
introduced the concept of type in ah_attr:
 * During ib_register_device, each port is checked for its type which
   is stored in ib_device's port_immutable array.
 * During uverbs' modify_qp, the type is inferred using the port number
   in ib_uverbs_qp_dest struct (address vector) by accessing the
   relevant port_immutable array and the type is passed on to
   providers.

IB spec (version 1.3) enforces a valid port value only in Reset to
Init. During Init to RTR, the address vector must be valid but port
number is not mentioned as a field in the address vector, so its
value is not validated, which leads to accesses to a non-allocated
memory when inferring the port type.

Save the real port number in ib_qp during modify to Init (when the
comp_mask indicates that the port number is valid) and use this value
to infer the port type.

Avoid copying the address vector fields if the matching bit is not set
in the attr_mask. Address vector can't be modified before the port, so
no valid flow is affected.

Fixes: 44c58487 ('IB/core: Define 'ib' and 'roce' rdma_ah_attr types')
Signed-off-by: NNoa Osherovich <noaos@mellanox.com>
Reviewed-by: NYishai Hadas <yishaih@mellanox.com>
Signed-off-by: NLeon Romanovsky <leon@kernel.org>
Signed-off-by: NDoug Ledford <dledford@redhat.com>
      498ca3c8
  11. 24 8月, 2017 2 次提交
    • L
      Revert "pty: fix the cached path of the pty slave file descriptor in the master" · 143c97cc
      由 Linus Torvalds 提交于 
      This reverts commit c8c03f18.

It turns out that while fixing the ptmx file descriptor to have the
correct 'struct path' to the associated slave pty is a really good
thing, it breaks some user space tools for a very annoying reason.

The problem is that /dev/ptmx and its associated slave pty (/dev/pts/X)
are on different mounts.  That was what caused us to have the wrong path
in the first place (we would mix up the vfsmount of the 'ptmx' node,
with the dentry of the pty slave node), but it also means that now while
we use the right vfsmount, having the pty master open also keeps the pts
mount busy.

And it turn sout that that makes 'pbuilder' very unhappy, as noted by
Stefan Lippers-Hollmann:

 "This patch introduces a regression for me when using pbuilder
  0.228.7[2] (a helper to build Debian packages in a chroot and to
  create and update its chroots) when trying to umount /dev/ptmx (inside
  the chroot) on Debian/ unstable (full log and pbuilder configuration
  file[3] attached).

  [...]
  Setting up build-essential (12.3) ...
  Processing triggers for libc-bin (2.24-15) ...
  I: unmounting dev/ptmx filesystem
  W: Could not unmount dev/ptmx: umount: /var/cache/pbuilder/build/1340/dev/ptmx: target is busy
          (In some cases useful info about processes that
           use the device is found by lsof(8) or fuser(1).)"

apparently pbuilder tries to unmount the /dev/pts filesystem while still
holding at least one master node open, which is arguably not very nice,
but we don't break user space even when fixing other bugs.

So this commit has to be reverted.

I'll try to figure out a way to avoid caching the path to the slave pty
in the master pty.  The only thing that actually wants that slave pty
path is the "TIOCGPTPEER" ioctl, and I think we could just recreate the
path at that time.
Reported-by: NStefan Lippers-Hollmann <s.l-h@gmx.de>
Cc: Eric W Biederman <ebiederm@xmission.com>
Cc: Christian Brauner <christian.brauner@canonical.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      143c97cc
    • O
      Revert "loop: support 4k physical blocksize" · 1e6ec9ea
      由 Omar Sandoval 提交于 
      There's some stuff still up in the air, let's not get stuck with a
subpar ABI. I'll follow up with something better for 4.14.
Signed-off-by: NOmar Sandoval <osandov@fb.com>
Signed-off-by: NJens Axboe <axboe@kernel.dk>
      1e6ec9ea
  13. 23 8月, 2017 5 次提交
  15. 22 8月, 2017 2 次提交
  17. 21 8月, 2017 3 次提交