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  1. 28 9月, 2006 2 次提交
  3. 14 9月, 2006 1 次提交
  5. 01 9月, 2006 4 次提交
  7. 30 8月, 2006 1 次提交
  9. 20 8月, 2006 1 次提交
  11. 17 8月, 2006 2 次提交
  13. 03 7月, 2006 1 次提交
  15. 01 7月, 2006 1 次提交
  17. 28 6月, 2006 1 次提交
  19. 09 6月, 2006 1 次提交
  21. 16 3月, 2006 1 次提交
  23. 05 3月, 2006 1 次提交
  25. 07 2月, 2006 1 次提交
  27. 18 1月, 2006 3 次提交
  29. 15 1月, 2006 1 次提交
  31. 13 1月, 2006 1 次提交
    • O
      [PATCH] corruption during e100 MDI register access · ac7c6669
      由 ODonnell, Michael 提交于 
      We have identified two related bugs in the e100 driver.

Both bugs are related to manipulation of the MDI control register.

The first problem is that the Ready bit is being ignored when writing to
the Control register; we noticed this because the Linux bonding driver
would occasionally come to the spurious conclusion that the link was down
when querying Link State.  It turned out that by failing to wait for a
previous command to complete it was selecting what was essentially a random
register in the MDI register set.  When we added code that waits for the
Ready bit (as shown in the patch file below) all such problems ceased.

The second problem is that, although access to the MDI registers involves
multiple steps which must not be intermixed, nothing was defending against
two or more threads attempting simultaneous access.  The most obvious
situation where such interference could occur involves the watchdog versus
ioctl paths, but there are probably others, so we recommend the locking
shown in our patch file.
Signed-off-by: NMichael O'Donnell <Michael.ODonnell@stratus.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jeff Garzik <jgarzik@pobox.com>
Cc: John Ronciak <john.ronciak@intel.com>
Cc: Ganesh Venkatesan <ganesh.venkatesan@intel.com>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>
      ac7c6669
  33. 19 11月, 2005 1 次提交
    • J
      [PATCH] e100: re-enable microcode with more useful defaults · 2afecc04
      由 Jesse Brandeburg 提交于 
      For the four versions of hardware that we (currently) support microcode
download on, the default configuration of our receive interrupt mitigation
microcode was too aggressive, and caused unnecessary delays when pinging,
and low(er) throughput on single connection latency sensitive performance
tests.

This code adds microcode support, and sets the defaults to more reasonable
settings. It also explains the functionality in the code in more detail.
Compile and load tested, shows expected behavior for slight delay of ping
packets (1-2ms) when ucode is loaded, and decent interrupt moderation for
small packets, while maintaining good throughput.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>
      2afecc04
  35. 08 11月, 2005 1 次提交
  37. 11 10月, 2005 1 次提交
    • J
      e100: revert CPU cycle saver microcode, it causes severe problems · 875521dd
      由 Jeff Garzik 提交于 
      for certain NICs

Reverting 685fac63:
> [PATCH] e100: CPU cycle saver microcode
>
>
> Add cpu cycle saver microcode to 8086:{1209/1229} other than ICH devices.
>
> Signed-off-by: Mallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com>
> Signed-off-by: Ganesh Venkatesan <ganesh.venkatesan@intel.com>
> Signed-off-by: John Ronciak <john.ronciak@intel.com>
> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
      875521dd
  39. 14 9月, 2005 2 次提交
  41. 26 8月, 2005 6 次提交
  43. 28 6月, 2005 1 次提交
  45. 27 6月, 2005 4 次提交
  47. 13 5月, 2005 1 次提交