1. 01 6月, 2007 2 次提交
  2. 12 5月, 2007 1 次提交
    • D
      Fix assertion failure with MSI on sparc64 · b3b7cc7b
      David Miller 提交于
      Today's find is a triggered assertion in msi_free_irqs() when the system
      doesn't support MSI, in which case arch_setup_msi_irqs() always returns
      an error.
      
      The problem is that when this happens we branch into msi_free_irqs(), to
      which you added the following assertion loop:
      
      	list_for_each_entry(entry, &dev->msi_list, list)
      		BUG_ON(irq_has_action(entry->irq));
      
      Well, if arch_setup_msi_irqs() fails, entry->irq will be zero and
      although that's never assigned to any normal devices we use that IRQ
      number for the timer interrupt on sparc64 so this assertion triggers.
      
      Better to test for zero before doing the irq_has_action() assertion
      thing.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      b3b7cc7b
  3. 09 5月, 2007 1 次提交
  4. 03 5月, 2007 18 次提交
  5. 04 4月, 2007 1 次提交
    • E
      [PATCH] msi: synchronously mask and unmask msi-x irqs. · 348e3fd1
      Eric W. Biederman 提交于
      This is a simplified and actually more comprehensive form of a bug
      fix from Mitch Williams <mitch.a.williams@intel.com>.
      
      When we mask or unmask a msi-x irqs the writes may be posted because
      we are writing to memory mapped region.  This means the mask and
      unmask don't happen immediately but at some unspecified time in the
      future.  Which is out of sync with how the mask/unmask logic work
      for ioapic irqs.
      
      The practical result is that we get very subtle and hard to track down
      irq migration bugs.
      
      This patch performs a read flush after writes to the MSI-X table for mask
      and unmask operations.  Since the SMP affinity is set while the interrupt
      is masked, and since it's unmasked immediately after, no additional flushes
      are required in the various affinity setting routines.
      
      The testing by Mitch Williams on his especially problematic system should
      still be valid as I have only simplified the code, not changed the
      functionality.
      
      We currently have 7 drivers: cciss, mthca, cxgb3, forceth, s2io,
      pcie/portdrv_core, and qla2xxx in 2.6.21 that are affected by this
      problem when the hardware they driver is plugged into the right slot.
      
      Given the difficulty of reproducing this bug and tracing it down to
      anything that even remotely resembles a cause, even if people are
      being affected we aren't likely to see many meaningful bug reports, and
      the people who see this bug aren't likely to be able to reproduce this
      bug in a timely fashion.  So it is best to get this problem fixed
      as soon as we can so people don't have problems.
      
      Then if people do have a kernel message stating "No irq for vector" we
      will know it is yet another novel cause that needs a complete new
      investigation.
      
      Cc: Greg KH <greg@kroah.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Signed-off-by: N"Eric W. Biederman" <ebiederm@xmission.com>
      Acked-by: NMitch Williams <mitch.a.williams@intel.com>
      Acked-by: N"Siddha, Suresh B" <suresh.b.siddha@intel.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      348e3fd1
  6. 13 3月, 2007 1 次提交
    • E
      [PATCH] msi: Safer state caching. · 392ee1e6
      Eric W. Biederman 提交于
      There are two ways pci_save_state and pci_restore_state are used.  As
      helper functions during suspend/resume, and as helper functions around
      a hardware reset event.  When used as helper functions around a hardware
      reset event there is no reason to believe the calls will be paired, nor
      is there a good reason to believe that if we restore the msi state from
      before the reset that it will match the current msi state.  Since arch
      code may change the msi message without going through the driver, drivers
      currently do not have enough information to even know when to call
      pci_save_state to ensure they will have msi state in sync with the other
      kernel irq reception data structures.
      
      It turns out the solution is straight forward, cache the state in the
      existing msi data structures (not the magic pci saved things) and
      have the msi code update the cached state each time we write to the hardware.
      This means we never need to read the hardware to figure out what the hardware
      state should be.
      
      By modifying the caching in this manner we get to remove our save_state
      routines and only need to provide restore_state routines.
      
      The only fields that were at all tricky to regenerate were the msi and msi-x
      control registers and the way we regenerate them currently is a bit dependent
      upon assumptions on how we use the allow msi registers to be configured and used
      making the code a little bit brittle.  If we ever change what cases we allow
      or how we configure the msi bits we can address the fragility then.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      Acked-by: NAuke Kok <auke-jan.h.kok@intel.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      392ee1e6
  7. 05 3月, 2007 3 次提交
    • E
      [PATCH] msi: support masking msi irqs without a mask bit · 58e0543e
      Eric W. Biederman 提交于
      For devices that do not support msi-x we only support 1 interrupt.  Therefore
      we can disable that one interrupt by disabling the msi capability itself.  If
      we leave the intx interrupts disabled while we have the msi capability
      disabled no interrupts should be delivered from that device.
      
      Devices with just the minimal msi support (and thus hitting this code path)
      include things like the intel e1000 nic, so it looks like is going to be a
      fairly common case and thus important to get right.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Michael Ellerman <michael@ellerman.id.au>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Greg KH <greg@kroah.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      58e0543e
    • E
      [PATCH] msi: fix up the msi enable/disable logic · b1cbf4e4
      Eric W. Biederman 提交于
      enable/disable_msi_mode have several side effects which keeps them from being
      generally useful.  So this patch replaces them with with two much more
      targeted functions: msi_set_enable and msix_set_enable.
      
      This patch makes pci_dev->msi_enabled and pci_dev->msix_enabled the definitive
      way to test if linux has enabled the msi capability, and has the appropriate
      msi data structures set up.
      
      This patch ensures that while writing the msi messages in save/restore and
      during device initialization we have the msi capability disabled so we don't
      get into races.  The pci spec requires that we do not have the msi capability
      enabled and the msi messages unmasked while we write the messages.  Completely
      disabling the capability is overkill but it is easy :)
      
      Care has been taken so we never have both a msi capability and intx enabled
      simultaneously.  We haven't run into a problem yet but better safe then sorry.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Michael Ellerman <michael@ellerman.id.au>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Greg KH <greg@kroah.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      b1cbf4e4
    • E
      [PATCH] msi: sanely support hardware level msi disabling · f5f2b131
      Eric W. Biederman 提交于
      In some cases when we are not using msi we need a way to ensure that the
      hardware does not have an msi capability enabled.  Currently the code has been
      calling disable_msi_mode to try and achieve that.  However disable_msi_mode
      has several other side effects and is only available when msi support is
      compiled in so it isn't really appropriate.
      
      Instead this patch implements pci_msi_off which disables all msi and msix
      capabilities unconditionally with no additional side effects.
      
      pci_disable_device was redundantly clearing the bus master enable flag and
      clearing the msi enable bit.  A device that is not allowed to perform bus
      mastering operations cannot generate intx or msi interrupt messages as those
      are essentially a special case of dma, and require bus mastering.  So the call
      in pci_disable_device to disable msi capabilities was redundant.
      
      quirk_pcie_pxh also called disable_msi_mode and is updated to use pci_msi_off.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Michael Ellerman <michael@ellerman.id.au>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Greg KH <greg@kroah.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      f5f2b131
  8. 08 2月, 2007 10 次提交
  9. 08 12月, 2006 2 次提交
  10. 19 10月, 2006 1 次提交