1. 31 1月, 2011 1 次提交
  2. 08 12月, 2010 2 次提交
  3. 02 10月, 2010 1 次提交
  4. 29 7月, 2010 3 次提交
  5. 16 2月, 2010 1 次提交
  6. 30 11月, 2008 1 次提交
  7. 01 10月, 2008 1 次提交
  8. 06 9月, 2008 1 次提交
    • L
      [ARM] 5241/1: provide ioremap_wc() · 1ad77a87
      Lennert Buytenhek 提交于
      This patch provides an ARM implementation of ioremap_wc().
      
      We use different page table attributes depending on which CPU we
      are running on:
      
      - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
        possible mapping types (CB=00/01/10/11).  We can't use any of the
        cached memory types (CB=10/11), since that breaks coherency with
        peripheral devices.  Both CB=00 and CB=01 are suitable for _wc, and
        CB=01 (Uncached/Buffered) allows the hardware more freedom than
        CB=00, so we'll use that.
      
        (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
        but isn't allowed to merge them, but there is no other mapping type
        we can use that allows the hardware to delay and merge stores, so
        we'll go with CB=01.)
      
      - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
        difference that on these platforms, CB=01 actually _does_ allow
        merging stores.  (If you want noncoalescing bufferable behavior
        on Xscale v1/v2, you need to use XCB=101.)
      
      - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
        mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
        in ARMv6 parlance).
      
        The ARMv6 ARM explicitly says that any accesses to Normal memory can
        be merged, which makes Normal memory more suitable for _wc mappings
        than Device or Strongly Ordered memory, as the latter two mapping
        types are guaranteed to maintain transaction number, size and order.
        We use the Uncached variety of Normal mappings for the same reason
        that we can't use C=1 mappings on ARMv5.
      
        The xsc3 Architecture Specification documents TEXCB=00100 as being
        Uncacheable and allowing coalescing of writes, which is also just
        what we need.
      Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      1ad77a87
  9. 07 8月, 2008 1 次提交
  10. 03 8月, 2008 1 次提交
  11. 15 10月, 2007 1 次提交
  12. 21 5月, 2007 1 次提交
  13. 06 5月, 2007 1 次提交
    • R
      [ARM] mm 10: allow memory type to be specified with ioremap · 3603ab2b
      Russell King 提交于
      __ioremap() took a set of page table flags (specifically the cacheable
      and bufferable bits) to control the mapping type.  However, with
      the advent of ARMv6, this is far too limited.
      
      Replace the page table flags with a memory type index, so that the
      desired attributes can be selected from the mem_type table.
      
      Finally, to prevent silent miscompilation due to the differing
      arguments, rename the __ioremap() and __ioremap_pfn() functions.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      3603ab2b
  14. 10 2月, 2007 1 次提交
  15. 30 11月, 2006 1 次提交
  16. 12 10月, 2006 1 次提交
  17. 09 10月, 2006 1 次提交
  18. 25 9月, 2006 1 次提交
  19. 28 8月, 2006 1 次提交
  20. 24 3月, 2006 1 次提交
  21. 10 1月, 2006 1 次提交
    • D
      [ARM] 3070/2: Add __ioremap_pfn() API · 9d4ae727
      Deepak Saxena 提交于
      Patch from Deepak Saxena
      
      In working on adding 36-bit addressed supersection support to ioremap(),
      I came to the conclusion that it would be far simpler to do so by just
      splitting __ioremap() into a main external interface and adding an
      __ioremap_pfn() function that takes a pfn + offset into the page that
      __ioremap() can call. This way existing callers of __ioremap() won't have
      to change their code and 36-bit systems will just call __ioremap_pfn()
      and we will not have to deal with unsigned long long variables.
      
      Note that __ioremap_pfn() should _NOT_ be called directly by drivers
      but is reserved for use by arch_ioremap() implementations that map
      32-bit resource regions into the real 36-bit address and then call
      this new function.
      Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      9d4ae727
  22. 05 12月, 2005 1 次提交
  23. 18 11月, 2005 1 次提交
  24. 28 10月, 2005 1 次提交
  25. 24 9月, 2005 1 次提交
  26. 27 6月, 2005 1 次提交
  27. 25 6月, 2005 1 次提交
  28. 21 6月, 2005 1 次提交
  29. 30 4月, 2005 1 次提交
    • O
      [PATCH] ARM: 2649/1: Fix 'sparse -Wbitwise' warnings from MMIO macros · 05f9869b
      Olav Kongas 提交于
      Patch from Olav Kongas
      
      On ARM, the outX() and writeX() families of macros take the
      result of cpu_to_leYY(), which is of restricted type __leYY,
      and feed it to __raw_writeX(), which expect an argument of
      unrestricted type. This results in 'sparse -Wbitwise'
      warnings about incorrect types in assignments. Analogous
      type mismatch warnings are issued for inX() and readX()
      counterparts. The below patch resolves these warnings by
      adding forced typecasts.
      
      Signed-off-by: Olav Kongas
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      05f9869b
  30. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4