Revert to change to a better code.

This reverts commit 55cef88b.
Signed-off-by: NYoshitaka Ikeda <ikeda@nskint.co.jp>
Link: https://lore.kernel.org/r/bd30bdb4-07c4-f713-5648-01c898d51f1b@nskint.co.jpSigned-off-by: NMark Brown <broonie@kernel.org>

Fix below division by zero warning:
- Added an if statement because buswidth can be zero, resulting in division by zero.
- The modified code was based on another driver (atmel-quadspi).

[    0.795337] Division by zero in kernel.
   :
[    0.834051] [<807fd40c>] (__div0) from [<804e1acc>] (Ldiv0+0x8/0x10)
[    0.839097] [<805f0710>] (cqspi_exec_mem_op) from [<805edb4c>] (spi_mem_exec_op+0x3b0/0x3f8)

Fixes: 7512eaf5 ("spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1")
Signed-off-by: NYoshitaka Ikeda <ikeda@nskint.co.jp>
Link: https://lore.kernel.org/r/ed989af6-da88-4e0b-9ed8-126db6cad2e4@nskint.co.jpSigned-off-by: NMark Brown <broonie@kernel.org>

When initialize cadence qspi controller, it is need to set cqspi
to the driver_data field of struct device, because it will be
used in function cqspi_remove/suspend/resume(). Otherwise, there
will be a crash trace as below when invoking these finctions.

Fixes: 31fb632b ("spi: Move cadence-quadspi driver to drivers/spi/")
Cc: stable@vger.kernel.org
Signed-off-by: NMeng Li <Meng.Li@windriver.com>
Link: https://lore.kernel.org/r/20210311091220.3615-1-Meng.Li@windriver.comSigned-off-by: NMark Brown <broonie@kernel.org>

drivers/spi/spi-cadence-quadspi.c:267:18: warning: Shifting signed 32-bit
value by 31 bits is undefined behaviour [shiftTooManyBitsSigned]
    return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
                    ^
Reported-by: Nkernel test robot <lkp@intel.com>
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NJay Fang <f.fangjian@huawei.com>
Link: https://lore.kernel.org/r/1614854872-8694-1-git-send-email-f.fangjian@huawei.comSigned-off-by: NMark Brown <broonie@kernel.org>

Fix OF node leaks by calling of_node_put in
for_each_available_child_of_node when the cycle returns.

Generated by: scripts/coccinelle/iterators/for_each_child.cocci
Signed-off-by: NJunlin Yang <yangjunlin@yulong.com>
Link: https://lore.kernel.org/r/20210215110425.1012-1-angkery@163.comSigned-off-by: NMark Brown <broonie@kernel.org>

Use the newly introduced spi_mem_dtr_supports_op() to check DTR op
support. This means the buswidth check does not need to be replicated.
It also happens to fix a bug where STR ops with a 2-byte opcode would be
reported as supported.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20210204141218.32229-2-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.
Signed-off-by: NRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-4-vadivel.muruganx.ramuthevar@linux.intel.comSigned-off-by: NMark Brown <broonie@kernel.org>

On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).

This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfe

DAC bit resets to 1 so there is no need to explicitly set it.
Signed-off-by: NRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-3-vadivel.muruganx.ramuthevar@linux.intel.comSigned-off-by: NMark Brown <broonie@kernel.org>

Add QSPI controller support for Intel LGM SoC.
Signed-off-by: NRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-2-vadivel.muruganx.ramuthevar@linux.intel.comSigned-off-by: NMark Brown <broonie@kernel.org>

The kernel test robot reports the following warning.

drivers/spi/spi-cadence-quadspi.c:966:24: warning: comparison of distinct pointer types ('typeof (len) *' (aka 'unsigned int *') and 'typeof (500UL) *' (aka 'unsigned long *')) [-Wcompare-distinct-pointer-types]
                                            msecs_to_jiffies(max(len, 500UL)))) {
                                                             ^~~~~~~~~~~~~~~
   include/linux/minmax.h:58:19: note: expanded from macro 'max'
   #define max(x, y)       __careful_cmp(x, y, >)
                           ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/minmax.h:42:24: note: expanded from macro '__careful_cmp'
           __builtin_choose_expr(__safe_cmp(x, y), \
                                 ^~~~~~~~~~~~~~~~
   include/linux/minmax.h:32:4: note: expanded from macro '__safe_cmp'
                   (__typecheck(x, y) && __no_side_effects(x, y))
                    ^~~~~~~~~~~~~~~~~
   include/linux/minmax.h:18:28: note: expanded from macro '__typecheck'
           (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
                      ~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~
   1 warning generated.

This happens because size_t is unsigned long on 64-bit platforms like
arm64 but it is unsigned int on 32-bit platforms like arm. Omitting the
"UL" would result in a warning on 64-bit platforms. Squash it by type
casting the arguments to size_t using max_t(). This way builds on both
type of platforms can be satisfied. There is no chance of any truncation
since 500 is small enough to fit into both int and long.

Fixes: f453f293 ("spi: cadence-quadspi: Wait at least 500 ms for direct reads")
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20210108181457.30291-1-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Fix a new warning report by build for make ARCH=MIPS allmodconfig:

drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_direct_read_execute':
 ./include/linux/minmax.h:18:28: warning: comparison of distinct pointer types lacks a cast
    18 |  (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
       |                            ^~
 ./include/linux/minmax.h:32:4: note: in expansion of macro '__typecheck'
    32 |   (__typecheck(x, y) && __no_side_effects(x, y))
       |    ^~~~~~~~~~~
 ./include/linux/minmax.h:42:24: note: in expansion of macro '__safe_cmp'
    42 |  __builtin_choose_expr(__safe_cmp(x, y), \
       |                        ^~~~~~~~~~
 ./include/linux/minmax.h:58:19: note: in expansion of macro '__careful_cmp'
    58 | #define max(x, y) __careful_cmp(x, y, >)
       |                   ^~~~~~~~~~~~~
 drivers/spi/spi-cadence-quadspi.c:1153:24: note: in expansion of macro 'max'
  1153 |       msecs_to_jiffies(max(len, 500UL)))) {
       |                        ^~~

"len" is unsigned,however,"500" is unsigned long.
Signed-off-by: NYanteng Si <siyanteng@loongson.cn>
Link: https://lore.kernel.org/r/20210107115704.3835282-1-siyanteng@loongson.cnSigned-off-by: NMark Brown <broonie@kernel.org>

Double Transfer Rate (DTR) mode transfers data twice per clock cycle.
Add support for parsing DTR ops and set up the registers to allow it.

Most SPI NOR flashes expect 2 byte commands. Parse the 2-byte opcode
from SPI MEM and set it up in the CQSPI_REG_OP_EXT_LOWER register.

Increment the delay needed before issuing indirect writes because larger
delay is needed for DTR mode. With the current delay some writes end up
missing.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-8-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

When performing a direct read via DMA the timeout for completion is set
equal to the read length. This is fine for larger reads. For a small
read like the Read Status Register command, the timeout would be 1 or 2
milliseconds. This is not enough to cover the overhead needed in setting
up DMA.

Make sure the timeout is at least 500 ms to allow DMA ample time to
finish. For reads larger than 500 bytes, the timeout will continue to be
equal to the read length.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Reported-by: Nkernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20201222184425.7028-7-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

The default SPI MEM supports_op hook rejects DTR ops by default. Add a
simple supports_op hook that very closely imitates the SPI MEM one. It
will be extended in later commits to allow DTR ops.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-6-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

SPI MEM deals with dummy bytes but the controller deals with dummy
cycles. Multiplying bytes by 8 is correct if the dummy phase uses 1S
mode since 1 byte will be sent in 8 cycles. But if the dummy phase uses
4S mode then 1 byte will be sent in 2 cycles.

To correctly translate dummy bytes to dummy cycles, the dummy buswidth
also needs to be taken into account. Divide 8 by the buswidth to get the
correct multiplier for getting the number of cycles.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-5-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

If a command does not have an address phase it goes via the STIG path.
The dummy cycles are not initialized for the STIG commands. As a result,
STIG commands with dummy cycles will not work.

Initialize the dummy cycle field before issuing the STIG command to make
sure it is sent correctly. Move the code to calculate dummy cycle value
to a separate function so it is not repeated twice. DTR support will add
some more logic here to it is worth it to extract it out in a function.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-4-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

The controller can only support up to 31 dummy cycles. If the command
requires more it falls back to using 31. This command is likely to fail
because the correct number of cycles are not waited upon. Rather than
silently issuing an incorrect command, fail loudly so the caller can get
a chance to find out the command can't be supported by the controller.

Fixes: 14062341 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-3-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

As of commit 9326e4f1 ("spi: Limit the spi device max speed to
controller's max speed"), the SPI device max speed is set to the
controller's max speed if it is larger. The Cadence QSPI controller does
not set the controller's max speed so it is left at its initial value of
0. This means the SPI device max speed is always set to 0.

The SPI device max speed is used to calculate the baud rate divider when
performing an operation. If this speed is 0, the default divider of 32
is used. No matter what speed is specified by the device tree property
'spi-max-frequency', the device will always operate at ref_clk / 32.

Fix this by setting master->max_speed_hz to the ref clock speed so the
correct divider can be calculated.
Signed-off-by: NPratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-2-p.yadav@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Fix to return the error code from
devm_reset_control_get_optional_exclusive() instaed of 0
in cqspi_probe().

Fixes: 31fb632b ("spi: Move cadence-quadspi driver to drivers/spi/")
Reported-by: NHulk Robot <hulkci@huawei.com>
Signed-off-by: NZhihao Cheng <chengzhihao1@huawei.com>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20201116141836.2970579-1-chengzhihao1@huawei.comSigned-off-by: NMark Brown <broonie@kernel.org>

Common pattern of handling deferred probe can be simplified with
dev_err_probe().  Less code and the error value gets printed.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200901152713.18629-5-krzk@kernel.orgSigned-off-by: NMark Brown <broonie@kernel.org>

Buffers need to mapped to DMA channel's device pointer instead of SPI
controller's device pointer as its system DMA that actually does data
transfer.
Data inconsistencies have been reported when reading from flash
without this fix.

Fixes: ffa639e0 ("mtd: spi-nor: cadence-quadspi: Add DMA support for direct mode reads")
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Tested-by: NJan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/20200831130720.4524-1-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Implement get_name() interface of spi_controller_mem_ops so as to avoid
changing of mtd->name due to driver being moved over to spi-mem
framework from SPI NOR. This avoids breaking of MTD cmdline args being
passed by bootloaders which maybe using old driver name.

Fixes: 31fb632b ("spi: Move cadence-quadspi driver to drivers/spi/")
Reported-by: NJan Kiszka <jan.kiszka@siemens.com>
Suggested-by: NBoris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200825172506.14375-1-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/

Update license header to match SPI subsystem style
Signed-off-by: NRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-9-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Move cadence-quadspi driver to use spi-mem framework. This is required
to make the driver support for SPI NAND flashes in future.

Driver is feature compliant with existing SPI NOR version.
Signed-off-by: NRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-8-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Drop redundant WREN command in cqspi_erase() as SPI NOR core takes care
of sending WREN command before sending erase command.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-7-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

dma_request_chan_by_mask() can throw EPROBE_DEFER if DMA provider
is not yet probed. Currently driver just falls back to using PIO mode
(which is less efficient) in this case. Instead return probe deferral
error as is so that driver will be re probed once DMA provider is
available.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-6-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-5-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-4-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Currently direct access mode is used on platforms that have AHB window
(memory mapped window) larger than flash size. This feature is limited
to TI platforms as non TI platforms have < 1MB of AHB window.
Therefore introduce a driver quirk to disable DAC mode and set it for
non TI compatibles. This is in preparation to move to spi-mem framework
where flash geometry cannot be known.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-3-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Drop configuration of Flash size, erase size and page size
configuration. Flash size is needed only if using AHB decoder (BIT 23 of
CONFIG_REG) which is not used by the driver.
Erase size and page size are needed if IP is configured to send WREN
automatically. But since SPI NOR layer takes care of sending WREN, there
is no need to configure these fields either.

Therefore drop these in preparation to move the driver to spi-mem
framework where flash geometry is not visible to controller driver.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-2-vigneshr@ti.comSigned-off-by: NMark Brown <broonie@kernel.org>

Move all SPI NOR controller drivers to a controllers/ sub-directory
so that we only have SPI NOR related source files under
drivers/mtd/spi-nor/.

Rename spi-nor.c into core.c, we are about to split this file in multiple
source files (one per manufacturer, plus one for the SFDP parsing logic).
Signed-off-by: NBoris Brezillon <bbrezillon@kernel.org>
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: NVignesh Raghavendra <vigneshr@ti.com>

The ops aren't used in any SPI NOR controller. Therefore, remove them
altogether.
Signed-off-by: NMichael Walle <michael@walle.cc>
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode',
to comply with the SPI NOR int (*read_reg)() method. The 'const'
qualifier has no meaning for parameters passed by value, drop it.
Going furher, the opcode was passed to cqspi_calc_rdreg() and never used,
drop it.
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: NBoris Brezillon <boris.brezillon@collabora.com>

Move all SPI NOR controller driver specific ops in a dedicated
structure. 'struct spi_nor' becomes lighter.

Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'.
Rename wite/read_buf to buf, the name of the functions are
suggestive enough. Constify buf in int (*write_reg). Comply with these
changes in the SPI NOR controller drivers.
Suggested-by: NBoris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: NBoris Brezillon <boris.brezillon@collabora.com>

We don't need dev_err() messages when platform_get_irq() fails now that
platform_get_irq() prints an error message itself when something goes
wrong. Let's remove these prints with a simple semantic patch.

// <smpl>
@@
expression ret;
struct platform_device *E;
@@

ret =
(
platform_get_irq(E, ...)
|
platform_get_irq_byname(E, ...)
);

if ( \( ret < 0 \| ret <= 0 \) )
{
(
-if (ret != -EPROBE_DEFER)
-{ ...
-dev_err(...);
-... }
|
...
-dev_err(...);
)
...
}
// </smpl>

While we're here, remove braces on if statements that only have one
statement (manually).

Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The current Cadence QSPI driver sometimes caused a
"rcu_sched self-detected stall" while writing large files.

Stall Report:
'# mtd_debug write /dev/mtd1 0 48816464 blob.img
[ 1815.454227] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1815.459789] rcu:     0-....: (2099 ticks this GP) idle=8c6/1/0x40000002
 softirq=6492/6492 fqs=935
[ 1815.468442] rcu:      (t=2100 jiffies g=8749 q=247)
	<snip> (abbreviated backtrace)
[ 1815.772086] [<c05a3ea0>] (cqspi_exec_flash_cmd) (cqspi_read_reg)
[ 1815.786203] [<c05a5488>] (cqspi_read_reg) from (read_sr)
[ 1815.803790] [<c05a0330>] (read_sr) from
	(spi_nor_wait_till_ready_with_timeout)
[ 1815.816610] [<c05a182c>] (spi_nor_wait_till_ready_with_timeout) from
	(spi_nor_write+0x104/0x1d0)
[ 1815.836791] [<c05a1a44>] (spi_nor_write) from (part_write+0x50/0x58)
	<snip>
[ 1815.997961] cadence-qspi ff809000.spi: Flash command execution timed out.
[ 1816.004733] error -110 reading SR
file_to_flash: write, size 0x2e8e150, n 0x2e8e150
write(): Connection timed out

This was caused by a tight loop in cqspi_wait_for_bit(). Fix by using
readl_relaxed_poll_timeout() which sleeps 10us while polling a register.

Fit onto 80 character line by truncating the bool clear parameter

Fixes: 14062341 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: NThor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

Get the reset control properties for the QSPI controller and bring them
out of reset. Most will have just one reset bit, but there is an additional
OCP reset bit that is used ECC. The OCP reset bit will also need to get
de-asserted as well. [1]

The reason this patch is needed is in the case where a bootloader leaves
the QSPI controller in a reset state, or a state where init cannot occur
successfully, the patch will put the QSPI controller into a clean state.

[1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.htmlSuggested-by: NTien-Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>
Reviewed-by: NVignesh Raghavendra <vigneshr@ti.com>
[tudor.ambarus@microchip.com: declare rstc and rstc_ocp on the same line]
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Reviewed-by: NSteve Winslow <swinslow@gmail.com>
Reviewed-by: NRichard Fontana <rfontana@redhat.com>
Reviewed-by: NAlexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

There is a spelling mistake in a dev_error message. Fix it.
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@collabora.com>

Cadence OSPI controller IP supports Octal IO (x8 IO lines),
It also has an integrated PHY. IP register layout is very
similar to existing QSPI IP except for additional bits to support Octal
and Octal DDR mode. Therefore, extend current driver to support Octal
mode. Only Octal SDR read (1-1-8)mode is supported for now.

Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@collabora.com>