1. 02 7月, 2019 1 次提交
  2. 21 5月, 2019 1 次提交
  3. 26 4月, 2019 1 次提交
  4. 08 4月, 2019 1 次提交
  5. 03 4月, 2019 1 次提交
    • W
      locking/rwsem: Remove rwsem-spinlock.c & use rwsem-xadd.c for all archs · 390a0c62
      Waiman Long 提交于
      Currently, we have two different implementation of rwsem:
      
       1) CONFIG_RWSEM_GENERIC_SPINLOCK (rwsem-spinlock.c)
       2) CONFIG_RWSEM_XCHGADD_ALGORITHM (rwsem-xadd.c)
      
      As we are going to use a single generic implementation for rwsem-xadd.c
      and no architecture-specific code will be needed, there is no point
      in keeping two different implementations of rwsem. In most cases, the
      performance of rwsem-spinlock.c will be worse. It also doesn't get all
      the performance tuning and optimizations that had been implemented in
      rwsem-xadd.c over the years.
      
      For simplication, we are going to remove rwsem-spinlock.c and make all
      architectures use a single implementation of rwsem - rwsem-xadd.c.
      
      All references to RWSEM_GENERIC_SPINLOCK and RWSEM_XCHGADD_ALGORITHM
      in the code are removed.
      Suggested-by: NPeter Zijlstra <peterz@infradead.org>
      Signed-off-by: NWaiman Long <longman@redhat.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Acked-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Davidlohr Bueso <dave@stgolabs.net>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tim Chen <tim.c.chen@linux.intel.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-c6x-dev@linux-c6x.org
      Cc: linux-m68k@lists.linux-m68k.org
      Cc: linux-riscv@lists.infradead.org
      Cc: linux-um@lists.infradead.org
      Cc: linux-xtensa@linux-xtensa.org
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: nios2-dev@lists.rocketboards.org
      Cc: openrisc@lists.librecores.org
      Cc: uclinux-h8-devel@lists.sourceforge.jp
      Link: https://lkml.kernel.org/r/20190322143008.21313-3-longman@redhat.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      390a0c62
  6. 26 2月, 2019 1 次提交
  7. 21 2月, 2019 1 次提交
  8. 20 2月, 2019 2 次提交
  9. 19 2月, 2019 1 次提交
    • Y
      32-bit userspace ABI: introduce ARCH_32BIT_OFF_T config option · 942fa985
      Yury Norov 提交于
      All new 32-bit architectures should have 64-bit userspace off_t type, but
      existing architectures has 32-bit ones.
      
      To enforce the rule, new config option is added to arch/Kconfig that defaults
      ARCH_32BIT_OFF_T to be disabled for new 32-bit architectures. All existing
      32-bit architectures enable it explicitly.
      
      New option affects force_o_largefile() behaviour. Namely, if userspace
      off_t is 64-bits long, we have no reason to reject user to open big files.
      
      Note that even if architectures has only 64-bit off_t in the kernel
      (arc, c6x, h8300, hexagon, nios2, openrisc, and unicore32),
      a libc may use 32-bit off_t, and therefore want to limit the file size
      to 4GB unless specified differently in the open flags.
      Signed-off-by: NYury Norov <ynorov@caviumnetworks.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NYury Norov <ynorov@marvell.com>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      942fa985
  10. 05 2月, 2019 1 次提交
    • B
      bpf, riscv: add BPF JIT for RV64G · 2353ecc6
      Björn Töpel 提交于
      This commit adds a BPF JIT for RV64G.
      
      The JIT is a two-pass JIT, and has a dynamic prolog/epilogue (similar
      to the MIPS64 BPF JIT) instead of static ones (e.g. x86_64).
      
      At the moment the RISC-V Linux port does not support
      CONFIG_HAVE_KPROBES, which means that CONFIG_BPF_EVENTS is not
      supported. Thus, no tests involving BPF_PROG_TYPE_TRACEPOINT,
      BPF_PROG_TYPE_PERF_EVENT, BPF_PROG_TYPE_KPROBE and
      BPF_PROG_TYPE_RAW_TRACEPOINT passes.
      
      The implementation does not support "far branching" (>4KiB).
      
      Test results:
        # modprobe test_bpf
        test_bpf: Summary: 378 PASSED, 0 FAILED, [366/366 JIT'ed]
      
        # echo 1 > /proc/sys/kernel/unprivileged_bpf_disabled
        # ./test_verifier
        ...
        Summary: 761 PASSED, 507 SKIPPED, 2 FAILED
      
      Note that "test_verifier" was run with one build with
      CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y and one without, otherwise
      many of the the tests that require unaligned access were skipped.
      
      CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y:
        # echo 1 > /proc/sys/kernel/unprivileged_bpf_disabled
        # ./test_verifier | grep -c 'NOTE.*unknown align'
        0
      
      No CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS:
        # echo 1 > /proc/sys/kernel/unprivileged_bpf_disabled
        # ./test_verifier | grep -c 'NOTE.*unknown align'
        59
      
      The two failing test_verifier tests are:
        "ld_abs: vlan + abs, test 1"
        "ld_abs: jump around ld_abs"
      
      This is due to that "far branching" involved in those tests.
      
      All tests where done on QEMU (QEMU emulator version 3.1.50
      (v3.1.0-688-g8ae951fbc106)).
      Signed-off-by: NBjörn Töpel <bjorn.topel@gmail.com>
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      2353ecc6
  11. 24 1月, 2019 1 次提交
  12. 08 1月, 2019 3 次提交
    • D
      riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig · 5aeb1b36
      David Abdurachmanov 提交于
      I looked into Documentation/trace/ftrace-design.rst and, I think,
      we check all the boxes needed for HAVE_SYSCALL_TRACEPOINTS.
      Signed-off-by: NDavid Abdurachmanov <david.abdurachmanov@gmail.com>
      Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      5aeb1b36
    • D
      riscv: add audit support · efe75c49
      David Abdurachmanov 提交于
      On RISC-V (riscv) audit is supported through generic lib/audit.c.
      The patch adds required arch specific definitions.
      Signed-off-by: NDavid Abdurachmanov <david.abdurachmanov@gmail.com>
      Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      efe75c49
    • Z
      RISC-V: Support MODULE_SECTIONS mechanism on RV32 · 2cffc956
      Zong Li 提交于
      This patch supports dynamic generate got and plt sections mechanism on
      rv32. It contains the modification as follows:
       - Always enable MODULE_SECTIONS (both rv64 and rv32)
       - Change the fixed size type.
      
      This patch had been tested by following modules:
      
      btrfs 6795991 0 - Live 0xa544b000
      test_static_keys 17304 0 - Live 0xa28be000
      zstd_compress 1198986 1 btrfs, Live 0xa2a25000
      zstd_decompress 608112 1 btrfs, Live 0xa24e7000
      lzo 8787 0 - Live 0xa2049000
      xor 27461 1 btrfs, Live 0xa2041000
      zram 78849 0 - Live 0xa2276000
      netdevsim 55909 0 - Live 0xa202d000
      tun 211534 0 - Live 0xa21b5000
      fuse 566049 0 - Live 0xa25fb000
      nfs_layout_flexfiles 192597 0 - Live 0xa229b000
      ramoops 74895 0 - Live 0xa2019000
      xfs 3973221 0 - Live 0xa507f000
      libcrc32c 3053 2 btrfs,xfs, Live 0xa34af000
      lzo_compress 17302 2 btrfs,lzo, Live 0xa347d000
      lzo_decompress 7178 2 btrfs,lzo, Live 0xa3451000
      raid6_pq 142086 1 btrfs, Live 0xa33a4000
      reed_solomon 31022 1 ramoops, Live 0xa31eb000
      test_bitmap 3734 0 - Live 0xa31af000
      test_bpf 1588736 0 - Live 0xa2c11000
      test_kmod 41161 0 - Live 0xa29f8000
      test_module 1356 0 - Live 0xa299e000
      test_printf 6024 0 [permanent], Live 0xa2971000
      test_static_key_base 5797 1 test_static_keys, Live 0xa2931000
      test_user_copy 4382 0 - Live 0xa28c9000
      xxhash 70501 2 zstd_compress,zstd_decompress, Live 0xa2055000
      Signed-off-by: NZong Li <zong@andestech.com>
      Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      2cffc956
  13. 22 12月, 2018 2 次提交
  14. 21 12月, 2018 1 次提交
  15. 14 12月, 2018 1 次提交
  16. 23 11月, 2018 2 次提交
  17. 01 11月, 2018 1 次提交
  18. 31 10月, 2018 2 次提交
  19. 23 10月, 2018 5 次提交
  20. 02 8月, 2018 3 次提交
  21. 05 7月, 2018 1 次提交
  22. 08 6月, 2018 1 次提交
    • L
      mm: introduce ARCH_HAS_PTE_SPECIAL · 3010a5ea
      Laurent Dufour 提交于
      Currently the PTE special supports is turned on in per architecture
      header files.  Most of the time, it is defined in
      arch/*/include/asm/pgtable.h depending or not on some other per
      architecture static definition.
      
      This patch introduce a new configuration variable to manage this
      directly in the Kconfig files.  It would later replace
      __HAVE_ARCH_PTE_SPECIAL.
      
      Here notes for some architecture where the definition of
      __HAVE_ARCH_PTE_SPECIAL is not obvious:
      
      arm
       __HAVE_ARCH_PTE_SPECIAL which is currently defined in
      arch/arm/include/asm/pgtable-3level.h which is included by
      arch/arm/include/asm/pgtable.h when CONFIG_ARM_LPAE is set.
      So select ARCH_HAS_PTE_SPECIAL if ARM_LPAE.
      
      powerpc
      __HAVE_ARCH_PTE_SPECIAL is defined in 2 files:
       - arch/powerpc/include/asm/book3s/64/pgtable.h
       - arch/powerpc/include/asm/pte-common.h
      The first one is included if (PPC_BOOK3S & PPC64) while the second is
      included in all the other cases.
      So select ARCH_HAS_PTE_SPECIAL all the time.
      
      sparc:
      __HAVE_ARCH_PTE_SPECIAL is defined if defined(__sparc__) &&
      defined(__arch64__) which are defined through the compiler in
      sparc/Makefile if !SPARC32 which I assume to be if SPARC64.
      So select ARCH_HAS_PTE_SPECIAL if SPARC64
      
      There is no functional change introduced by this patch.
      
      Link: http://lkml.kernel.org/r/1523433816-14460-2-git-send-email-ldufour@linux.vnet.ibm.comSigned-off-by: NLaurent Dufour <ldufour@linux.vnet.ibm.com>
      Suggested-by: NJerome Glisse <jglisse@redhat.com>
      Reviewed-by: NJerome Glisse <jglisse@redhat.com>
      Acked-by: NDavid Rientjes <rientjes@google.com>
      Cc: Michal Hocko <mhocko@kernel.org>
      Cc: "Aneesh Kumar K . V" <aneesh.kumar@linux.vnet.ibm.com>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
      Cc: Rich Felker <dalias@libc.org>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Albert Ou <albert@sifive.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: David Rientjes <rientjes@google.com>
      Cc: Robin Murphy <robin.murphy@arm.com>
      Cc: Christophe LEROY <christophe.leroy@c-s.fr>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      3010a5ea
  23. 05 6月, 2018 1 次提交
    • A
      perf: riscv: preliminary RISC-V support · 178e9fc4
      Alan Kao 提交于
      This patch provide a basic PMU, riscv_base_pmu, which supports two
      general hardware event, instructions and cycles.  Furthermore, this
      PMU serves as a reference implementation to ease the portings in
      the future.
      
      riscv_base_pmu should be able to run on any RISC-V machine that
      conforms to the Priv-Spec.  Note that the latest qemu model hasn't
      fully support a proper behavior of Priv-Spec 1.10 yet, but work
      around should be easy with very small fixes.  Please check
      https://github.com/riscv/riscv-qemu/pull/115 for future updates.
      
      Cc: Nick Hu <nickhu@andestech.com>
      Cc: Greentime Hu <greentime@andestech.com>
      Signed-off-by: NAlan Kao <alankao@andestech.com>
      Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      178e9fc4
  24. 19 5月, 2018 3 次提交
  25. 09 5月, 2018 2 次提交