1. 23 3月, 2021 1 次提交
  2. 18 3月, 2021 2 次提交
  3. 10 3月, 2021 7 次提交
  4. 13 2月, 2021 1 次提交
    • R
      of: Remove of_dev_{get,put}() · 83c4a4ee
      Rob Herring 提交于
      of_dev_get() and of_dev_put are just wrappers for get_device()/put_device()
      on a platform_device. There's also already platform_device_{get,put}()
      wrappers for this purpose. Let's update the few users and remove
      of_dev_{get,put}().
      
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Jakub Kicinski <kuba@kernel.org>
      Cc: Frank Rowand <frowand.list@gmail.com>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Cc: Felipe Balbi <balbi@kernel.org>
      Cc: Julia Lawall <Julia.Lawall@inria.fr>
      Cc: Gilles Muller <Gilles.Muller@inria.fr>
      Cc: Nicolas Palix <nicolas.palix@imag.fr>
      Cc: Michal Marek <michal.lkml@markovi.net>
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: netdev@vger.kernel.org
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-usb@vger.kernel.org
      Cc: cocci@systeme.lip6.fr
      Signed-off-by: NRob Herring <robh@kernel.org>
      Reviewed-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      Link: https://lore.kernel.org/r/20210211232745.1498137-2-robh@kernel.org
      83c4a4ee
  5. 09 2月, 2021 2 次提交
  6. 06 2月, 2021 5 次提交
  7. 05 2月, 2021 2 次提交
  8. 04 2月, 2021 2 次提交
  9. 15 1月, 2021 4 次提交
  10. 14 1月, 2021 2 次提交
  11. 12 1月, 2021 3 次提交
  12. 07 1月, 2021 1 次提交
  13. 04 1月, 2021 5 次提交
  14. 28 12月, 2020 3 次提交
    • S
      usb: dwc3: ulpi: Fix USB2.0 HS/FS/LS PHY suspend regression · e5f4ca3f
      Serge Semin 提交于
      First of all the commit e0082698 ("usb: dwc3: ulpi: conditionally
      resume ULPI PHY") introduced the Suspend USB2.0 HS/FS/LS PHY regression,
      as by design of the fix any attempt to read/write from/to the PHY control
      registers will completely disable the PHY suspension, which consequently
      will increase the USB bus power consumption. Secondly the fix won't work
      well for the very first attempt of the ULPI PHY control registers IO,
      because after disabling the USB2.0 PHY suspension functionality it will
      still take some time for the bus to resume from the sleep state if one has
      been reached before it. So the very first PHY register read/write
      operation will take more time than the busy-loop provides and the IO
      timeout error might be returned anyway.
      
      Here we suggest to fix the denoted problems in the following way. First of
      all let's not disable the Suspend USB2.0 HS/FS/LS PHY functionality so to
      make the controller and the USB2.0 bus more power efficient. Secondly
      instead of that we'll extend the PHY IO op wait procedure with 1 - 1.2 ms
      sleep if the PHY suspension is enabled (1ms should be enough as by LPM
      specification it is at most how long it takes for the USB2.0 bus to resume
      from L1 (Sleep) state). Finally in case if the USB2.0 PHY suspension
      functionality has been disabled on the DWC USB3 controller setup procedure
      we'll compensate the USB bus resume process latency by extending the
      busy-loop attempts counter.
      
      Fixes: e0082698 ("usb: dwc3: ulpi: conditionally resume ULPI PHY")
      Acked-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
      Signed-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
      Link: https://lore.kernel.org/r/20201210085008.13264-4-Sergey.Semin@baikalelectronics.ru
      Cc: stable <stable@vger.kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      e5f4ca3f
    • S
      usb: dwc3: ulpi: Replace CPU-based busyloop with Protocol-based one · fca3f138
      Serge Semin 提交于
      Originally the procedure of the ULPI transaction finish detection has been
      developed as a simple busy-loop with just decrementing counter and no
      delays. It's wrong since on different systems the loop will take a
      different time to complete. So if the system bus and CPU are fast enough
      to overtake the ULPI bus and the companion PHY reaction, then we'll get to
      take a false timeout error. Fix this by converting the busy-loop procedure
      to take the standard bus speed, address value and the registers access
      mode into account for the busy-loop delay calculation.
      
      Here is the way the fix works. It's known that the ULPI bus is clocked
      with 60MHz signal. In accordance with [1] the ULPI bus protocol is created
      so to spend 5 and 6 clock periods for immediate register write and read
      operations respectively, and 6 and 7 clock periods - for the extended
      register writes and reads. Based on that we can easily pre-calculate the
      time which will be needed for the controller to perform a requested IO
      operation. Note we'll still preserve the attempts counter in case if the
      DWC USB3 controller has got some internals delays.
      
      [1] UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1,
          October 20, 2004, pp. 30 - 36.
      
      Fixes: 88bc9d19 ("usb: dwc3: add ULPI interface support")
      Acked-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
      Signed-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
      Link: https://lore.kernel.org/r/20201210085008.13264-3-Sergey.Semin@baikalelectronics.ru
      Cc: stable <stable@vger.kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      fca3f138
    • S
      usb: dwc3: ulpi: Use VStsDone to detect PHY regs access completion · ce722da6
      Serge Semin 提交于
      In accordance with [1] the DWC_usb3 core sets the GUSB2PHYACCn.VStsDone
      bit when the PHY vendor control access is done and clears it when the
      application initiates a new transaction. The doc doesn't say anything
      about the GUSB2PHYACCn.VStsBsy flag serving for the same purpose. Moreover
      we've discovered that the VStsBsy flag can be cleared before the VStsDone
      bit. So using the former as a signal of the PHY control registers
      completion might be dangerous. Let's have the VStsDone flag utilized
      instead then.
      
      [1] Synopsys DesignWare Cores SuperSpeed USB 3.0 xHCI Host Controller
          Databook, 2.70a, December 2013, p.388
      
      Fixes: 88bc9d19 ("usb: dwc3: add ULPI interface support")
      Acked-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
      Signed-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
      Link: https://lore.kernel.org/r/20201210085008.13264-2-Sergey.Semin@baikalelectronics.ru
      Cc: stable <stable@vger.kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      ce722da6