Received official word finally from Technological Systems on which
FPGA ID's they have released unto the world.  Also an additional of
a dummy entry matching the FPGA ID of the Verilog template on our
wiki.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Fix some typos in the DNS-323 support code.
Signed-off-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Stefan Agner found his board comes with 0x00b480/0x02 but the main
board also has Rev B printed on it like my 0x00b480/0x03.  Some light
enum renaming was needed but it was to be expected.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

This data should be passed to the xor driver in order to initialize
the address decoding windows of the xor unit. without this patch, the
self tests of the xor will fail unless the address decoding windows were
initialized by the boot loader.
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

ts78xx add NAND support via plat_nand
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

amend RTC registering to not depend on ifdef's
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

Added checks to the platform_device_(register|add) calls so that if
a device failed to load it would then not later be unloaded; also
added the hooks so that it would not try to unload when the RTC
driver support is compiled out.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

The GPIO interrupts can be configured as either level triggered or edge
triggered, with a default of level triggered.  When an edge triggered
interrupt is requested, the gpio_irq_set_type method is called which
currently switches the given IRQ descriptor between two struct irq_chip
instances: orion_gpio_irq_level_chip and orion_gpio_irq_edge_chip. This
happens via __setup_irq() which also calls irq_chip_set_defaults() to
assign default methods to uninitialized ones.  The problem is that
irq_chip_set_defaults() is called before the irq_chip reference is
switched, leaving the new irq_chip (orion_gpio_irq_edge_chip in this
case) with uninitialized methods such as chip->startup() causing a kernel
oops.

Many solutions are possible, such as making irq_chip_set_defaults() global
and calling it from gpio_irq_set_type(), or calling __irq_set_trigger()
before irq_chip_set_defaults() in __setup_irq().  But those require
modifications to the generic IRQ code which might have adverse effect on
other architectures, and that would still be a fragile arrangement.
Manually copying the missing methods from within gpio_irq_set_type()
would be really ugly and it would break again the day new methods with
automatic defaults are added.

A better solution is to have a single irq_chip instance which can deal
with both edge and level triggered interrupts.  It is also a good idea
to switch the IRQ handler instead, as the edge IRQ handler allows for
one edge IRQ event to be queued as the IRQ is actually masked only when
that second IRQ is received, at which point the hardware can queue an
additional IRQ event, making edge triggered interrupts a bit more
reliable.
Tested-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

the FPGA on the TS-7800 provides access to a number of devices
and so we have to be careful when reprogramming it.  As we
are effectively turning a bus off/on we have to inform the
kernel that it should stop using anything provided by the
FPGA (currently only the RTC however the NAND, LCD, etc is
to come) before it's reprogrammed.

Once reprogramed, we can tell the kernel to (re)enable things
by checking the FPGA ID against a lookup table for what a
particular FPGA bitstream can provide.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

moved the MPP comments to the mpp area of the platform code
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

The TS-7800's M25P40 is not available to the kernel, it's used
to load the initial bitstream onto the FPGA and so these hooks
point to nothing and need to be removed.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

Commit ba84be23 broke the build.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Split off Orion GPIO IRQ handling code into plat-orion/.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Split off Orion GPIO handling code into plat-orion/, and add
support for multiple sets of (32) GPIO pins.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

The 88F5182 found in the DNS-323 rev B1 (and some other devices, such
as the CH3SNAS) require different initialisation of the SATA
controller and MPP registers.

Tested on a DNS-323 rev B1.
Signed-off-by: NMatt Palmer <mpalmer@hezmatt.org>

Based on similar code from the tsx09 series of machines, just rips the MAC
address out of flash and stuffs it into the NIC. Tested on a DNS323 rev B1.
It's possible (though unlikely) that an A1 will have the MAC in a different
location in flash.
Signed-off-by: NMatt Palmer <mpalmer@hezmatt.org>

The Orion ehci driver serves the Orion, kirkwood and DD Soc families.
Since each of those integrate a different USB phy we should have the
ability to use few initialization sequences or to leave the boot loader
phy settings as is.
Signed-off-by: NRonen Shitrit <rshitrit@marvell.com>

As Al did for Versatile in 2ad4f86b,
add a typesafe __io implementation for platforms to use.  Convert
platforms to use this new simple typesafe implementation.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

When ISA_DMA_API is unset, we're not implementing the ISA DMA API,
so there's no point in publishing the prototypes via asm/dma.h, nor
including the machine dependent parts of that API.

This allows us to remove a lot of mach/dma.h files which don't contain
any useful code.  Unfortunately though, some platforms put their own
private non-ISA definitions into mach/dma.h, so we leave these behind
and fix the appropriate #include statments.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Let's provide an overridable default instead of having every machine
class define __virt_to_bus and __bus_to_virt to the same thing.  What
most platforms are using is bus_addr == phys_addr so such is the default.

One exception is ebsa110 which has no DMA what so ever, so the actual
definition is not important except only for proper compilation.  Also
added a comment about the special footbridge bus translation.

Let's also remove comments alluding to set_dma_addr which is not
(and should not) be commonly used.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

According to the documentation gpio_free should only be called from task
context only.  To make this more explicit add a might sleep to all
implementations.

This patch changes the gpio_free implementations for the arm architecture.
 DaVinci is skipped on purpose to simplify the merge process for patches
switching it over to use gpiolib as per request by David Brownell.
Signed-off-by: NUwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Cc: David Brownell <david-b@pacbell.net>
Cc: Andrew Victor <linux@maxim.org.za>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Commit 2ede90ca78500ca0ffeee19d7812d345f8ad152d adds 6183 support,
but the SPI support in there doesn't work since it depends on a
6183 SPI unit erratum fix that only just went upstream, via commit
2bec19fe.
Signed-off-by: NNicolas Pitre <nico@marvell.com>

This adds DSA switch instantiation hooks to the orion5x and the
kirkwood ARM SoC platform code, and instantiates the DSA switch
driver on the 88F5181L FXO RD, the 88F5181L GE RD, the 6183 AP GE
RD, the Linksys WRT350n v2, and the 88F6281 RD boards.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Tested-by: NNicolas Pitre <nico@marvell.com>
Tested-by: NPeter van Valderen <linux@ddcrew.com>
Tested-by: NDirk Teurlings <dirk@upexia.nl>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

This patch allows the use of the hardware watchdog in the
Marvell Orion series of ARM SoCs.
Signed-off-by: NSylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

desc_handle_irq() was declared as obsolete since long ago.
Replace it with generic_handle_irq()
Signed-off-by: NDmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds specific power-off method for Buffalo Linkstation Mini
board. The board has a hardware switch which should be monitored from
userspace. When the switch is in OFF position the board should be rebooted
and U-Boot will start in an idle mode and wait for the user to move the
power switch back to ON position.
Signed-off-by: NAlexey Kopytko <alexey@kopytko.ru>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

This patch adds support for Buffalo Linkstation Mini board.
Signed-off-by: NAlexey Kopytko <alexey@kopytko.ru>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

This patch provides standard GPIO LED control
for the ED Mini V2, with software blinking only
(CPLD hardware blinking capability is not used).

This patch also provides status of the power
button as a standard GPIO input event.
Signed-off-by: NAlbert Aribaud <albert.aribaud@free.fr>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

The RD88F6183AP-GE is an access point reference design for the
88F6183 SoC, with a 88E6161 six-port gigabit ethernet switch with
five PHYs (providing 1 WAN and 4 LAN ports and an interface to the
CPU), and a mini-PCIe slot for a wireless card.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This patch adds support for the Buffalo Terastation Pro II/Live.
Signed-off-by: NSylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This patch adds support for the LaCie Ethernet Disk mini V2.
Signed-off-by: NAlbert Aribaud <albert.aribaud@free.fr>
Signed-off-by: NChristopher Moore <moore@free.fr>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Currently, orion5x uses a hardcoded timer tick rate of 166 MHz, but
the actual timer tick rate varies between different members of the SoC
family (and can vary based on strap pin settings).

This patch prepares for runtime determination of the timer tick rate.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Wire up the ethernet port's error interrupt so that the
mv643xx_eth driver can sleep for SMI event completion instead of
having to busy-wait for it.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Currently, there are two different fields in the
mv643xx_eth_platform_data struct that together describe the PHY
address -- one field (phy_addr) has the address of the PHY, but if
that address is zero, a second field (force_phy_addr) needs to be
set to distinguish the actual address zero from a zero due to not
having filled in the PHY address explicitly (which should mean
'use the default PHY address').

If we are a bit smarter about the encoding of the phy_addr field,
we can avoid the need for a second field -- this patch does that.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Register UART1 on QNAP TS-209 and TS-409 because the PIC controller
is connected to it.  This fixes a regression from 2.6.26.
Signed-off-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The lm75 driver was recently converted to the new-style binding,
so now it can be loaded from the DNS-323 support code.
Signed-off-by: NMartin Michlmayr <tbm@cyrius.com>
Tested-by: NTobias Poschwatta <tp@fonz.de>
Acked-by: NBen Dooks <ben-linux@fluff.org>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Flash needs to be set up before we can try to read the MAC address
from there.
Signed-off-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The Kurobox Pro crashes when any of the PCI controller registers
are accessed.  This patch adds a function to the Orion PCI handling
code that board support code can call to disable enumerating the
PCI bus entirely, and makes the Kurobox Pro PCI-related init code
call this function.
Signed-off-by: NPer Andersson <avtobiff@gmail.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>