The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver.

By leveraging the gpio-regmap API, the i8255 library is reduced to
simply a devm_i8255_regmap_register() function, a configuration
structure struct i8255_regmap_config, and a helper macro
i8255_volatile_regmap_range() provided to simplify volatile PPI register
hinting for the regmap.

Legacy functions and code will be removed once all consumers have
migrated to the new i8255 library interface.
Suggested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver. Despite the underlying interface being based on
i8255, it is simpler to use the gpio-regmap API directly because the
104-IDI-48 device features only input signals. Therefore, the dependence
on the i8255 GPIO library is removed in this patch.
Suggested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver.

For the 104-idi-48, we get an IRQ register with some status information
and basic masking, but it's broken down by banks rather than individual
GPIO. There are six banks (8 GPIO lines each) that correspond to the
lower six bits of the IRQ register (bits 0-5):

    Base Address + 7 (Read): IRQ Status Register/IRQ Clear
        Bit 0-5: Respective Bank IRQ Statuses
        Bit 6: IRQ Status (Active Low)
        Bit 7: IRQ Enable Status
    Base Address + 7 (Write): IRQ Enable/Disable
        Bit 0-5: Respective Bank IRQ Enable/Disable
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver.

For the 104-dio-48e we have the following IRQ registers (0xB and 0xF):

    Base Address +B (Write): Enable Interrupt
    Base Address +B (Read): Disable Interrupt
    Base Address +F (Read/Write): Clear Interrupt

Any write to 0xB will enable interrupts, while any read will disable
interrupts. Interrupts are cleared by a write to 0xF. There's no IRQ
status register, so software has to assume that if an interrupt is
raised then it was for the 104-DIO-48E device.
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

Added module build support for the davinci gpio driver
Signed-off-by: NGuillaume La Roque <glaroque@baylibre.com>
Signed-off-by: NNicolas Frayer <nfrayer@baylibre.com>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

Add support for HiSilicon GPIO controller in embedded platform, which
boot from devicetree.
Signed-off-by: NWeilong Chen <chenweilong@huawei.com>
Acked-by: NJay Fang <f.fangjian@huawei.com>
Reviewed-by: NYicong Yang <yangyicong@hisilicon.com>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

This driver implements a GPIO multiplexer based on latches connected to
other GPIOs. A set of data GPIOs is connected to the data input of
multiple latches. The clock input of each latch is driven by another
set of GPIOs. With two 8-bit latches 10 GPIOs can be multiplexed into
16 GPIOs. GPOs might be a better term as in fact the multiplexed pins
are output only.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NSerge Semin <fancer.lancer@gmail.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
[Bartosz: fixed the strange of_device_id formatting]
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

The ACCES PCI-IDIO-16 device is part of the ACCES IDIO-16 family, so the
idio-16 GPIO library module is selected and utilized to consolidate
code.
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

The ACCES 104-IDIO-16 device is part of the ACCES IDIO-16 family, so the
idio-16 GPIO library module is selected and utilized to consolidate
code.
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

Exposes consumer library functions to facilitate communication with
devices within the ACCES IDIO-16 family such as the 104-IDIO-16 and
the PCI-IDIO-16.

A CONFIG_GPIO_IDIO_16 Kconfig option is introduced by this patch.
Modules wanting access to these idio-16 library functions should select
this Kconfig option and import the GPIO_IDIO_16 symbol namespace.

Cc: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

The Connext chip has 4 gpio cells looking very similar to those of the
Nomadik, whose gpio/pinctrl driver (already featuring devicetree support)
will be used instead of the sta2x11 specific one.
Signed-off-by: NDavide Ciminaghi <ciminaghi@gnudd.com>
Acked-by: NGiancarlo Asnaghi <giancarlo.asnaghi@st.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: NBartosz Golaszewski <bartosz.golaszewski@linaro.org>

Add GPIO support for Nuvoton NCT6116 chip. Nuvoton SuperIO chips are
very similar to the ones from Fintek. In other subsystems they also
share drivers and are called a family of drivers.

For the GPIO subsystem the only difference is that the direction bit is
reversed and that there is only one data bit per pin. On the SuperIO
level the logical device is another one.

On a chip level we do not have a manufacturer ID to check and also no
revision.
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NSimon Guinot <simon.guinot@sequanux.org>
Signed-off-by: NHenning Schild <henning.schild@siemens.com>
Acked-by: NBartosz Golaszewski <brgl@bgdev.pl>
Link: https://lore.kernel.org/r/20220825104422.14156-4-henning.schild@siemens.comSigned-off-by: NHans de Goede <hdegoede@redhat.com>

The SCU firmware on i.MX8 platforms provides a set of APIs to
control the GPIO PINs on the SCU domain. This patch implements the
standard GPIO driver interface to access those PINs on the
SCU domain over the SCU APIs.
Signed-off-by: NShenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

With commit 9d2b2e83 ("Input: adp5588-keys - support gpi key events as
'gpio keys'") the irchip functionality is directly supported in the input
driver as the main goal of these pins is to be used as gpio keys. Hence,
this driver can be removed.
Signed-off-by: NNuno Sá <nuno.sa@analog.com>
Acked-by: NBartosz Golaszewski <brgl@bgdev.pl>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220829131553.690063-3-nuno.sa@analog.comSigned-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>

Reduce magic numbers and improve code readability by implementing and
utilizing named register data structures. The GPIO-MM device features an
Intel 8255 compatible GPIO interface, so the i8255 GPIO module is
selected and utilized as well.
Tested-by: NFred Eckert <Frede@cmslaser.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

Reduce magic numbers and improve code readability by implementing and
utilizing named register data structures. The 104-IDI-48 device features
an Intel 8255 compatible GPIO interface, so the i8255 GPIO module is
selected and utilized as well.
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: John Hentges <jhentges@accesio.com>
Cc: Jay Dolan <jay.dolan@accesio.com>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

Reduce magic numbers and improve code readability by implementing and
utilizing named register data structures. The 104-DIO-48E device
features an Intel 8255 compatible GPIO interface, so the i8255 GPIO
module is selected and utilized as well.
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: John Hentges <jhentges@accesio.com>
Cc: Jay Dolan <jay.dolan@accesio.com>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

Exposes consumer library functions providing support for interfaces
compatible with the venerable Intel 8255 Programmable Peripheral
Interface (PPI).

The Intel 8255 PPI first appeared in the early 1970s, initially for the
Intel 8080 and later appearing in the original IBM-PC. The popularity of
the original Intel 8255 chip led to many subsequent variants and clones
of the interface in various chips and integrated circuits. Although
still popular, interfaces compatible with the Intel 8255 PPI are
nowdays typically found embedded in larger VLSI processing chips and
FPGA components rather than as discrete ICs.

A CONFIG_GPIO_I8255 Kconfig option is introduced by this patch. Modules
wanting access to these i8255 library functions should select this
Kconfig option, and import the I8255 symbol namespace.
Tested-by: NFred Eckert <Frede@cmslaser.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: John Hentges <jhentges@accesio.com>
Cc: Jay Dolan <jay.dolan@accesio.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NWilliam Breathitt Gray <william.gray@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

Commit d3164e2f ("MIPS: Remove VR41xx support") removed support
for MIPS VR41xx platform, so remove exclusive drivers for this
platform, too.
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
Acked-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

The SAMA5D2 PIOBU is only present on some AT91/Microchip SoCs.  Hence
add a dependency on ARCH_AT91, to prevent asking the user about this
driver when configuring a kernel without AT91/Microchip SoC support.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

i.MX7ULP, i.MX8 and i.MX9 use this driver, so drop
the SOC_VF610 dependcy to make the driver could be built
for i.MX platform.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

The boardfiles for IXP4xx have been deleted. Delete all the
quirks and code dealing with that boot path and rely solely on
device tree boot.

Fix some missing static keywords that the kernel test robot
was complaining about while we're at it.

Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Acked-by: NMarc Zyngier <maz@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

There are some special clock amendments for two machines
formerly detected by their machine_is() boardfile macro.

They are now migrated to device tree so use
of_machine_is_compatible() instead.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

Delta TN48M switch has an onboard Lattice CPLD that is used as a GPIO
expander.

The CPLD provides 12 pins in total on the TN48M, but on more advanced
switch models it provides up to 192 pins, so the driver is extendable
to support more switches.
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NBartosz Golaszewski <brgl@bgdev.pl>
Signed-off-by: NRobert Marko <robert.marko@sartura.hr>
Link: https://lore.kernel.org/r/20220131133049.77780-3-robert.marko@sartura.hrSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
GPIOs. Each instance in DT is for a single bank.
Acked-by: NBartosz Golaszewski <brgl@bgdev.pl>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NFelix Fietkau <nbd@nbd.name>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

The gpio-tps68470 driver binds to a tps68470-gpio platform-device which
itself gets instantiated by a special MFD driver from
drivers/platform/x86/intel/int3472/tps68470.c

This MFD driver itself can be built as a module, so it makes no sense to
force the gpio-tps68470 driver to always be built-in.
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>

Implement a new, modern GPIO testing module controlled by configfs
attributes instead of module parameters. The goal of this driver is
to provide a replacement for gpio-mockup that will be easily extensible
with new features and doesn't require reloading the module to change
the setup.
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

The only known BD70528 use-cases are such that the PMIC is controlled
from separate MCU which is not running Linux. I am not aware of
any Linux driver users. Furthermore, it seems there is no demand for
this IC. Let's ease the maintenance burden and drop the driver. We can
always add it back if there is sudden need for it.
Signed-off-by: NMatti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/4eff6bd5eff8afc137dd8c1697cb5c6b2e3aacd2.1637066805.git.matti.vaittinen@fi.rohmeurope.com

gpio-rockchip uses interfaces that are provided by the Kconfig
symbol GENERIC_IRQ_CHIP, so the driver should select that symbol
in order to prevent build errors.

Fixes these build errors (and more):

aarch64-linux-ld: drivers/gpio/gpio-rockchip.o: in function `rockchip_irq_disable':
gpio-rockchip.c:(.text+0x454): undefined reference to `irq_gc_mask_set_bit'
aarch64-linux-ld: drivers/gpio/gpio-rockchip.o: in function `rockchip_irq_enable':
gpio-rockchip.c:(.text+0x478): undefined reference to `irq_gc_mask_clr_bit'
aarch64-linux-ld: drivers/gpio/gpio-rockchip.o: in function `rockchip_interrupts_register':
gpio-rockchip.c:(.text+0x518): undefined reference to `irq_generic_chip_ops'
aarch64-linux-ld: gpio-rockchip.c:(.text+0x594): undefined reference to `__irq_alloc_domain_generic_chips'
aarch64-linux-ld: gpio-rockchip.c:(.text+0x5cc): undefined reference to `irq_get_domain_generic_chip'
aarch64-linux-ld: gpio-rockchip.c:(.text+0x5e0): undefined reference to `irq_gc_ack_set_bit'
aarch64-linux-ld: gpio-rockchip.c:(.text+0x604): undefined reference to `irq_gc_set_wake'

Fixes: 936ee267 ("gpio/rockchip: add driver for rockchip gpio")
Signed-off-by: NRandy Dunlap <rdunlap@infradead.org>
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

Netlogic XLP was removed in commit 95b8a5e0 ("MIPS: Remove NETLOGIC
support"). With those gone, the single platform left to support is
Cavium ThunderX2. Remove all the Netlogic variants and DT support.

For simplicity, the existing kconfig name is retained.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: NRob Herring <robh@kernel.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

This patch adds IRQ support for the virtio GPIO driver. Note that this
uses the irq_bus_lock/unlock() callbacks, since those operations over
virtio may sleep.
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

Fix multiple problems in punctuation, capitalization, grammar,
wording, and typos in the GPIO Kconfig file.
Signed-off-by: NRandy Dunlap <rdunlap@infradead.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Cc: linux-gpio@vger.kernel.org
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Sean Young <sean@mess.org>
Cc: Bamvor Jian Zhang <bamv2005@gmail.com>
Cc: Michael Walle <michael@walle.cc>
Acked-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

This patch adds driver support for the zynqmp modepin GPIO controller.
GPIO modepin driver set and get the value and status of the PS_MODE pin,
based on device-tree pin configuration. These four mode pins are
configurable as input/output. The mode pin has a control register, which
have lower four-bits [0:3] are configurable as input/output, next four-bits
can be used for reading the data  as input[4:7], and next setting the
output pin state output[8:11]. By default value of mode pin register is 0.
Signed-off-by: NPiyush Mehta <piyush.mehta@xilinx.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NBartosz Golaszewski <brgl@bgdev.pl>

Commit e1324ece ("ARM: imx: Remove i.MX35 board files") removes the
config MACH_MX35_3DS in arch/arm/mach-imx/Kconfig.

Hence, since then, the MX35 3DS BOARD MC9S08DZ60 GPIO functions are dead
code as its config GPIO_MC9S08DZ60 depends on the config MACH_MX35_3DS.

Luckily, ./scripts/checkkconfigsymbols.py warns on non-existing configs:

MACH_MX35_3DS
Referencing files: drivers/gpio/Kconfig

Remove the obsolete MX35 3DS BOARD MC9S08DZ60 GPIO functions.
Signed-off-by: NLukas Bulwahn <lukas.bulwahn@gmail.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

This patch adds a new driver for Virtio based GPIO devices.

This allows a guest VM running Linux to access GPIO lines provided by
the host. It supports all basic operations, except interrupts for the
GPIO lines.

Based on the initial work posted by:
"Enrico Weigelt, metux IT consult" <lkml@metux.net>.
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

This patch add support for rockchip gpio controller, which is supported
in pinctrl driver in the past.

With this patch, the pinctrl-rockchip driver will drop gpio related
codes and populate platform driver to gpio-rockchip.
Signed-off-by: NJianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210816012053.1119069-1-jay.xu@rock-chips.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Both of these drivers use ioport_map(), so they need to
depend on HAS_IOPORT_MAP. Otherwise, they cannot be built
even with COMPILE_TEST on architectures without an ioport
implementation, such as ARCH=um.
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

This driver only covered one scenario in which ACPI devices with _HID
INT3472 are found, and its functionality has been taken over by the
intel-skl-int3472 module, so remove it.
Acked-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: NLee Jones <lee.jones@linaro.org>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NDaniel Scally <djrscally@gmail.com>
Link: https://lore.kernel.org/r/20210603224007.120560-7-djrscally@gmail.comSigned-off-by: NHans de Goede <hdegoede@redhat.com>

IDT 79RC3243x SoCs integrated a gpio controller, which handles up
to 32 gpios. All gpios could be used as an interrupt source.
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

Driver is neither dependent to PCI nor using MFD_CORE.
Replace those dependency and selection by dependency on LPC_ICH.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>