1. 03 9月, 2014 3 次提交
  2. 20 8月, 2014 3 次提交
  3. 13 8月, 2014 2 次提交
    • D
      drm/i915: Only track real ppgtt for a context · ae6c4806
      Daniel Vetter 提交于
      There's a bit a confusion since we track the global gtt,
      the aliasing and real ppgtt in the ctx->vm pointer. And not
      all callers really bother to check for the different cases and just
      presume that it points to a real ppgtt.
      
      Now looking closely we don't actually need ->vm to always point at an
      address space - the only place that cares actually has fixup code
      already to decide whether to look at the per-proces or the global
      address space.
      
      So switch to just tracking the ppgtt directly and ditch all the
      extraneous code.
      
      v2: Fixup the ppgtt debugfs file to not oops on a NULL ctx->ppgtt.
      Also drop the early exit - without aliasing ppgtt we want to dump all
      the ppgtts of the contexts if we have full ppgtt.
      
      v3: Actually git add the compile fix.
      Reviewed-by: NMichel Thierry <michel.thierry@intel.com>
      Cc: "Thierry, Michel" <michel.thierry@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      OTC-Jira: VIZ-3724
      [danvet: Resolve conflicts with execlist patches while applying.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ae6c4806
    • D
      drm/i915: Track file_priv, not ctx in the ppgtt structure · 4d884705
      Daniel Vetter 提交于
      Hardware contexts reference a ppgtt, not the other way round. And the
      only user of this (in debugfs) actually only cares about which file
      the ppgtt is associated with. So give it what it wants.
      
      While at it give the ppgtt create function a proper name&place.
      Reviewed-by: NMichel Thierry <michel.thierry@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4d884705
  4. 09 8月, 2014 1 次提交
  5. 08 8月, 2014 2 次提交
    • D
      drm/i915: Introduce a for_each_intel_encoder() macro · b2784e15
      Damien Lespiau 提交于
      Following the established idom, let's provide a macro to iterate through
      the encoders.
      
      spatch helps, once more, for the substitution:
      
        @@
        iterator name list_for_each_entry;
        iterator name for_each_intel_encoder;
        struct intel_encoder * encoder;
        struct drm_device * dev;
        @@
        -list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
        +for_each_intel_encoder(dev, encoder) {
          ...
        }
      
      I also modified a few call sites by hand where a pointer to mode_config
      was directly used (to avoid overflowing 80 chars).
      Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
      [danvet: Wrap paramters correctly in the macro and remove spurious
      space checkpatch noticed.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      b2784e15
    • R
      drm/i915: Introduce FBC False Color for debug purposes. · da46f936
      Rodrigo Vivi 提交于
      With this bit enabled, HW changes the color when compressing frames for
      debug purposes.
      
      ALthough the simple way to enable a single bit is over intel_reg_write,
      this value is overwriten on next update_fbc so depending on the workload
      it is not possible to set this bit with intel-gpu-tools. So this patch
      introduces a persistent way to enable false color over debugfs.
      
      v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
      v3: (Ville) only do false color for IVB+ since according to spec bit is
          MBZ before IVB.
      v4: We don't have FBC on valleyview nor on cherryview (Ben)
      v5: s/!HAS_PCH_SPLIT/!HAS_FBC (Ville)
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      da46f936
  6. 23 7月, 2014 5 次提交
  7. 22 7月, 2014 1 次提交
  8. 21 7月, 2014 1 次提交
  9. 11 7月, 2014 4 次提交
  10. 10 7月, 2014 1 次提交
  11. 09 7月, 2014 4 次提交
  12. 08 7月, 2014 5 次提交
    • O
      drm/i915: Emphasize that ctx->id is merely a user handle · 821d66dd
      Oscar Mateo 提交于
      This is an Execlists preparatory patch, since they make context ID become an
      overloaded term:
      
      - In the software, it was used to distinguish which context userspace was
        trying to use.
      - In the BSpec, the term is used to describe the 20-bits long field the
        hardware uses to it to discriminate the contexts that are submitted to
        the ELSP and inform the driver about their current status (via Context
        Switch Interrupts and Context Status Buffers).
      
      Initially, I tried to make the different meanings converge, but it proved
      impossible:
      
      - The software ctx->id is per-filp, while the hardware one needs to be
        globally unique.
      - Also, we multiplex several backing states objects per intel_context,
        and all of them need unique HW IDs.
      - I tried adding a per-filp ID and then composing the HW context ID as:
        ctx->id + file_priv->id + ring->id, but the fact that the hardware only
        uses 20-bits means we have to artificially limit the number of filps or
        contexts the userspace can create.
      
      The ctx->user_handle renaming bits are done with this Cocci patch (plus
      manual frobbing of the struct declaration):
      
          @@
          struct intel_context c;
          @@
          - (c).id
          + c.user_handle
      
          @@
          struct intel_context *c;
          @@
          - (c)->id
          + c->user_handle
      
      Also, while we are at it, s/DEFAULT_CONTEXT_ID/DEFAULT_CONTEXT_HANDLE and
      change the type to unsigned 32 bits.
      
      v2: s/handle/user_handle and change the type to uint32_t as suggested by
      Chris Wilson.
      
      Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1)
      Signed-off-by: NOscar Mateo <oscar.mateo@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      821d66dd
    • O
      drm/i915: Emphasize that ctx->obj & ctx->is_initialized refer to the legacy rcs ctx · ea0c76f8
      Oscar Mateo 提交于
      We have already advanced that Logical Ring Contexts have their own kind
      of backing objects, but everything will be better explained in the Execlists
      series. For now, suffice it to say that the current backing object is only
      ever used with the render ring, so we're making this fact more explicit
      (which is a good reason on its own).
      
      As for the is_initialized flag, we only use to signify that the render state
      has been initialized (a.k.a. golden context, a.k.a. null context). It doesn't
      mean anything for the other engines, so make that distinction obvious.
      
      Done with the following Coccinelle patch (plus manual frobbing of the struct):
      
          @@
          struct intel_context c;
          @@
          - (c).obj
          + c.legacy_hw_ctx.rcs_state
      
          @@
          struct intel_context *c;
          @@
          - (c)->obj
          + c->legacy_hw_ctx.rcs_state
      
          @@
          struct intel_context c;
          @@
          - (c).is_initialized
          + c.legacy_hw_ctx.initialized
      
          @@
          struct intel_context *c;
          @@
          - (c)->is_initialized
          + c->legacy_hw_ctx.initialized
      
      This Execlists prep-work patch has been suggested by Chris Wilson and Daniel
      Vetter separately.
      
      Initially, it was two separate patches:
      drm/i915: Rename ctx->obj to ctx->rcs_state
      drm/i915: Make it obvious that ctx->id is merely a user handle
      Signed-off-by: NOscar Mateo <oscar.mateo@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      [danvet: s/id/is_initialized/ to fix the subject and resolve a
      conflict in i915_gem_context_reset. Also introduce a new lctx local
      variable to avoid overtly long lines.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ea0c76f8
    • B
      drm/i915: semaphore debugfs · e04934cf
      Ben Widawsky 提交于
      Simple debugfs file to display the current state of semaphores. This is
      useful if you want to see the state without hanging the GPU.
      
      NOTE: This patch is optional to the series.
      
      NOTE2: Like the GPU error state collection, the reads are currently
      incoherent.
      
      v2 (Rodrigo): * Iterate only on active rings.
         	      * s/ring_buffer/engine_cs.
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      e04934cf
    • D
      drm/i915: Support pf CRC source on haswell transcoder edp · fabf6e51
      Daniel Vetter 提交于
      The always-on power well pixel path on haswell is routed such that it
      bypasses the panel fitter when we use is. Which means the pfit CRC
      source won't work in that configuration.
      
      Add a new disallow-bypass flags to the pfit pipe config state and set
      it when we want to use the pf CRC. Results in a bit of flicker, but
      should get the job done. We'll also undo do it afterwards to make sure
      other tests arent' negatively affected.
      
      Totally untested due to lack of hsw laptops around here.
      
      v2: s/disallow_bypass/force_power_well_on/ to avoid a double negative
      (Damien).
      
      v3: force_thru because roadsigns.
      
      v4: Don't forget the power wells! Also note that until the runtime pm
      for DPMS series is fully merged the simple disable/enable trick won't
      work since the ->crtc_mode_set callback is still required to do nasty
      things. This stuff is tricky, but I think by both fixing up
      get_crtc_power_domains and the debugfs wa code we should always
      grab/drop the additional power well correctly.
      
      v5: Wrap in () as suggested by Damien to avoid setting reserved values
      for the edp transcoder path on bdw+
      
      References: https://bugs.freedesktop.org/show_bug.cgi?id=72864
      Cc: Damien Lespiau <damien.lespiau@intel.com>
      Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com>
      Tested-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      fabf6e51
    • R
      drm/i915: Don't pretend ips is always enabled on BDW. · 0eaa53f0
      Rodrigo Vivi 提交于
      As pointed out before we don't have a reliable way to read back ips
      status on BDW without the risk to disable it when reading.
      However now we are pretending that IPS on BDW is always on and getting
      people confused about it.
      
      So this patch allows people to know if ips was ever attempted to be enabled.
      Even if the current status is impossible to be ascertain.
      
      v2: (spotted by Paulo):
           * A version that at least compiles
           * with more clear messages
           * let Cheryview on the safe side until we aren't sure that checking ips
             state on ips won't disable it.
      
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      0eaa53f0
  13. 04 7月, 2014 1 次提交
  14. 24 6月, 2014 1 次提交
    • C
      drm/i915: Hold the table lock whilst walking the file's idr and counting the objects in debugfs · 5b5ffff0
      Chris Wilson 提交于
      Fixes an issue whereby we may race with the table updates (before the
      core takes the struct_mutex) and so risk dereferencing a stale pointer in
      the iterator for /debugfs/.../i915_gem_objects. For example,
      
      [ 1524.757545] BUG: unable to handle kernel paging request at f53af748
      [ 1524.757572] IP: [<c1406982>] per_file_stats+0x12/0x100
      [ 1524.757599] *pdpt = 0000000001b13001 *pde = 00000000379fb067 *pte = 80000000353af060
      [ 1524.757621] Oops: 0000 [#1] SMP DEBUG_PAGEALLOC
      [ 1524.757637] Modules linked in: ctr ccm arc4 ath9k ath9k_common ath9k_hw ath snd_hda_codec_conexant mac80211 snd_hda_codec_generic snd_hda_intel snd_hda_controller snd_hda_codec bnep snd_hwdep rfcomm snd_pcm gpio_ich dell_wmi sparse_keymap snd_seq_midi hid_multitouch uvcvideo snd_seq_midi_event dell_laptop snd_rawmidi dcdbas snd_seq videobuf2_vmalloc videobuf2_memops videobuf2_core usbhid videodev snd_seq_device coretemp snd_timer hid joydev kvm_intel cfg80211 ath3k kvm btusb bluetooth serio_raw snd microcode soundcore lpc_ich wmi mac_hid parport_pc ppdev lp parport psmouse ahci libahci
      [ 1524.757825] CPU: 3 PID: 1911 Comm: intel-gpu-overl Tainted: G        W  OE 3.15.0-rc3+ #96
      [ 1524.757840] Hardware name: Dell Inc. Inspiron 1090/Inspiron 1090, BIOS A06 08/23/2011
      [ 1524.757855] task: f52f36c0 ti: f4cbc000 task.ti: f4cbc000
      [ 1524.757869] EIP: 0060:[<c1406982>] EFLAGS: 00210202 CPU: 3
      [ 1524.757884] EIP is at per_file_stats+0x12/0x100
      [ 1524.757896] EAX: 0000002d EBX: 00000000 ECX: f4cbdefc EDX: f53af700
      [ 1524.757909] ESI: c1406970 EDI: f53af700 EBP: f4cbde6c ESP: f4cbde5c
      [ 1524.757922]  DS: 007b ES: 007b FS: 00d8 GS: 0033 SS: 0068
      [ 1524.757934] CR0: 80050033 CR2: f53af748 CR3: 356af000 CR4: 000007f0
      [ 1524.757945] Stack:
      [ 1524.757957]  f4cbdefc 00000000 c1406970 f53af700 f4cbdea8 c12e5f15 f4cbdefc c1406970
      [ 1524.757993]  0000ffff f4cbde90 0000002d f5dc5cd0 e4e80438 c1181d59 f4cbded8 f4d89900
      [ 1524.758027]  f5631b40 e5131074 c1903f37 f4cbdf28 c14068e6 f52648a0 c1927748 c1903f37
      [ 1524.758062] Call Trace:
      [ 1524.758084]  [<c1406970>] ? i915_gem_object_info+0x510/0x510
      [ 1524.758106]  [<c12e5f15>] idr_for_each+0xa5/0x100
      [ 1524.758126]  [<c1406970>] ? i915_gem_object_info+0x510/0x510
      [ 1524.758148]  [<c1181d59>] ? seq_vprintf+0x29/0x50
      [ 1524.758168]  [<c14068e6>] i915_gem_object_info+0x486/0x510
      [ 1524.758189]  [<c11823a6>] seq_read+0xd6/0x380
      [ 1524.758208]  [<c116d11d>] ? final_putname+0x1d/0x40
      [ 1524.758227]  [<c11822d0>] ? seq_hlist_next_percpu+0x90/0x90
      [ 1524.758246]  [<c1163e52>] vfs_read+0x82/0x150
      [ 1524.758265]  [<c11645d6>] SyS_read+0x46/0x90
      [ 1524.758285]  [<c16b8d8c>] sysenter_do_call+0x12/0x22
      [ 1524.758298] Code: f5 8f 2a 00 83 c4 6c 31 c0 5b 5e 5f 5d c3 8d 74 26 00 8d bc 27 00 00 00 00 55 89 e5 57 56 53 83 ec 04 3e 8d 74 26 00 83 41 04 01 <8b> 42 48 01 41 08 8b 42 4c 89 d7 85 c0 75 07 8b 42 60 85 c0 74
      [ 1524.758461] EIP: [<c1406982>] per_file_stats+0x12/0x100 SS:ESP 0068:f4cbde5c
      [ 1524.758485] CR2: 00000000f53af748
      Reported-by: NSam Jansen <sam.jansen@starleaf.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Sam Jansen <sam.jansen@starleaf.com>
      Cc: stable@vger.kernel.org
      Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      5b5ffff0
  15. 19 6月, 2014 1 次提交
  16. 18 6月, 2014 1 次提交
  17. 17 6月, 2014 1 次提交
  18. 14 6月, 2014 1 次提交
  19. 13 6月, 2014 2 次提交