This adds missing kernel-doc entries for cs_gpios in struct spi_master and
cs_gpio in struct spi_device.
Signed-off-by: NAndreas Larsson <andreas@gaisler.com>
[grant.likely: tweaked the language of the descriptions]
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Using memset does not set an array of integers properly. Replace with a
loop to set each element properly.
Signed-off-by: NAndreas Larsson <andreas@gaisler.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Intel Lynxpoint PCH Low Power Subsystem has two general purpose SPI
controllers that are LPSS_SSP compatible. These controllers are enumerated
from ACPI namespace with ACPI IDs INT33C0 and INT33C1.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Intel LPSS SPI is pretty much the same as the PXA27xx SPI except that it
has few additional features over the original:

	o FIFO depth is 256 entries
	o RX FIFO has one watermark
	o TX FIFO has two watermarks, low and high
	o chip select can be controlled by writing to a register

The new FIFO registers follow immediately the PXA27xx registers but then there
are some additional LPSS private registers at offset 1k or 2k from the base
address. For these private registers we add new accessors that take advantage
of drv_data->lpss_base once it is resolved.

We add a new type LPSS_SSP that can be used to distinguish the LPSS devices
from others.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This is useful when testing the functionality of the controller from userspace
and there aren't any real SPI slave devices connected to the bus.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Drivers should put the device into low power states proactively whenever the
device is not in use. Thus implement support for runtime PM and use the
autosuspend feature to make sure that we can still perform well in case we see
lots of SPI traffic within short period of time.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

To be able to use DMA with this driver on non-PXA platforms we implement
support for the generic DMA engine API. This lets user to use different DMA
engines with little or no modification to the driver.

Request lines and channel numbers can be passed to the driver from the
platform specific data.

The DMA engine implementation will be selected by default even on PXA
platform. User can select the legacy DMA API by enabling Kconfig option
CONFIG_SPI_PXA2XX_PXADMA.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The PXA SPI driver uses PXA platform specific private DMA implementation
which does not work on non-PXA platforms. In order to use this driver on
other platforms we break out the private DMA implementation into a separate
file that gets compiled only when CONFIG_SPI_PXA2XX_PXADMA is set. The DMA
functions are stubbed out if there is no DMA implementation selected (i.e
we are building on non-PXA platform).

While we are there we can kill the dummy DMA bits in pxa2xx_spi.h as they
are not needed anymore for CE4100.

Once this is done we can add the generic DMA engine support to the driver
that allows usage of any DMA controller that implements DMA engine API.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The SPI controller of the AR7xxx/AR9xxx SoCs
have a special mode which allows the SoC to
directly read data from SPI flash chips. In
this mode, the content of the SPI flash chip
can be accessed via a memory mapped region.

During early init time, the kernel expects
that the flash chip is accessible through
that memory region because it reads board
specific values (e.g. MAC address, WiFi
calibration data) from the flash on various
boards.

This is working if the kernel is loaded
directly by the bootloader because that
leaves the SPI controller in the special
mode. However it is not working in a kexec'd
kernel because the SPI driver does not restore
the special mode during shutdown.

The patch adds a shutdown handler to fix this
issue.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Due to hardware limitations of the spi/flash frontend of the EBU we need to set
the SPI_MASTER_HALF_DUPLEX flag.
Signed-off-by: NThomas Langer <thomas.langer@lantiq.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Rather than calling m->complete() directly we choose the sane way and call
spi_finalize_current_message instead.
Signed-off-by: NThomas Langer <thomas.langer@lantiq.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This SPI controller does not support keeping CS asserted after sending
a transfer.
Since messages expected on this SPI controller are rather short, we can
work around it for normal use cases by sending all transfers at once in
a big full duplex stream.

This means that we cannot change the speed between transfers if they
require CS to be kept asserted, but these would have been rejected
before anyway because of the inability of keeping CS asserted.
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

With RT pre-empt patch applied to Linux kernel, the irq handler will be
force converted to an irq thread. spi driver can get back to back messages
from the slave device. In such cases, IRQ thread doesn't get a chance to
run to read the slave data. Hence the irq handler must be run in hard irq
context to read/write data from slave device. Otherwise, the kernel goes
into a deadlock. This patch fixes this issue when PREEMPT_RT_FULL is
enabled in the kernel. A dummy thread function is provided to satisfy the
request_threaded_irq() API. Passing a NULL for function also causes the
irq handler to be executed in the thread context.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch reduces and simplifies initalization code by
using module_platform_driver().
With this change it's necessary to remove the __init annotation
to avoid section mismatch warnings.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The hardware does not support keeping CS asserted after sending one
FIFO buffer worth of data, so reject transfers requiring CS being kept
asserted, either between transers or for a certain time after it,
or exceeding the FIFO size.
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Acked-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Use GFP_DMA in order to ensure that the memory we allocate for transfers
in spi_write_then_read() can be DMAed. On most platforms this will have
no effect.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The driver should setup mode bits it supports, otherwise
adding an SPI device might fail even if the driver supports
the requested SPI mode.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Remove deprecated cell-index property and use spi alias to
obtain the SPI PSC number used for SPI bus id.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Some of the spi driver module remove hooks were annotated with __exit
and referenced with __exit_p(). Presumably these were supposed to be
__devinit, __devexit and __devexit_p() since __init/__exit for a
probe/remove hook has never been correct. They also got missed during
the big __devinit/__devexit purge since they didn't match the pattern.
Remove then now to be rid of it.

v2: purge __init also
Reported-by: NArnd Bergmann <arnd@arndb.de>
[Arnd set a patch cleaning up one, and then I found more]
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Fix checkpatch warnings and error as below:
  ERROR: "foo * bar" should be "foo *bar"
  WARNING: please, no space before tabs
  WARNING: quoted string split across lines
  WARNING: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Use devm_clk_get() and devm_request_irq() rather than clk_get() and
request_irq() to make cleanup paths more simple.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add an entry for MODULE_ALIAS().
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

SPI core make sure that all transfer has proper speed set
before calling low level spi transfer. Hence, it is not
require to have check in spi driver.

Remove the check for speed validity from transfer and use it directly.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

When spi client does the spi transfer and if it does not set
the speed for each transfer then set it as default
of spi device in spi core before calling low level transfer.

This will remove the extra check in low level driver for setting
speed.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Currently we are initializing the SPI controller in
the chip select line function, and that function is
called once for each SPI device on the bus. If a
board has multiple SPI devices, the controller will
be initialized multiple times.

Introduce ath79_spi_{en,dis}able helper functions,
and call those from probe/response in order to avoid
the mutliple initialization of the controller.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Use gpio_request_one() instead of multiple gpiolib calls.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The spi_bitbang driver calls the chipselect function
of the driver from spi_bitbang_setup in order to
deselect the given SPI chip, so we don't have to
initialize the CS line here.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The 'ath79_spi_txrx_mode0' function does not
set the SCK signal to LOW at the end of a word
transfer. This causes communications errors with
certain devices (e.g. the PCF2123 RTC chip).

The patch ensures that the SCK signal will be LOW.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The driver uses the "as fast as it can" approach
to drive the SCK signal. However this does not
work with certain low speed SPI chips (e.g. the
PCF2123 RTC chip).

The patch adds per-bit slowdowns in order to be
able to use the driver with such chips as well.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

On MX23 the XFER_COUNT part in ctrl0 field in DMA descriptor was
improperly OR'd during the construction of DMA descriptor chain, instead
of being freshly set.  Because of that too many bytes were being
expected from SPI during the last DMA cycle.  This caused a timeout
(SSP_TIMEOUT) to happen in the processing of the last DMA descriptor,
and thus reads and writes were failing.  This is a fix for the problem,
by clearing XFER_COUNT bytes in ctrl0 before setting the new XFER_COUNT
for DMA descriptor.
Signed-off-by: NJuha Lumme <juha.lumme@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

the driver is also compatible with SiRFmarco except SiRFprimaII,
so simply add "sirf,marco-spi" to OF match table.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Convert clk_enable/clk_disable to clk_prepare_enable/clk_disable_unprepare
calls as required by common clock framework.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Minor features and bug fixes for PXA, OMAP and GPIO deivce drivers and a
cosmetic change to the bitbang driver.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The spi core make sure that each transfer structure have the proper
setting for bits_per_word before calling low level transfer APIs.

Hence it is no more require to check again in low level driver for
this field whether this is set correct or not. Removing such code
from low level driver.

The txx9 change also removes a test for bits_per_word set to 0, and
forcing it to 8 in that case. This can also be removed now since
spi_setup() ensures spi->bits_per_word is not zero.

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Linux assigns a number to each spi_master in the system, but when the
platform used the device tree, the numbers are dynamically assigned and
are not predictable. In general this shouldn't matter since the kernel
doesn't use the bus number for anything other than matching a bus to
spi_boardinfo (not used for DT). However, sometimes userspace needs to
figure out which bus is which, so it makes sense to use the global
/aliases namespace to choose a specific bus number.

It is safe to derive the bus number from an alias because aliases will
never cause two buses to try and use the same bus number. (At one time
the cell-index property was used for this purpose, but cell-index has
the risk of an id collision).
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>

This adds the capability to retrieve setup data from the device tree
node. The usage of platform data is still available.
Signed-off-by: NBastian Hecht <hechtb+renesas@gmail.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This adds OF support to DaVinci SPI controller to configure platform
data through device bindings. Also replaces clk_enable() with
of clk_prepare_enable() as well as clk_disable() with
clk_disable_unprepare().
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

No actual errors have been found for completing
before disabling DMA request lines, but it just
looks more semantically correct that on our DMA
callback we quiesce the whole thing before stating
transfer is finished.
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>