This limitation maybe had some reason in the past, but now there is not
one -> removing this.
Signed-off-by: NJiri Pirko <jiri@resnulli.us>
Acked-by: NVeaceslav Falico <vfalico@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Rip out a bunch of redundant PCI-E Memory Window Read/Write routines,
collapse the more general purpose routines into a single routine
thereby eliminating the need for a large stack frame (and extra data
copying) in the outer routine, change everything to use the improved
routine t4_memory_rw.

Based on origninal work by Casey Leedom <leedom@chelsio.com> and
Steve Wise <swise@opengridcomputing.com>
Signed-off-by: NCasey Leedom <leedom@chelsio.com>
Signed-off-by: NSteve Wise <swise@opengridcomputing.com>
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Use the firmware interface to get the BAR0 value since we really don't want
to use the PCI-E Configuration Space Backdoor access which is owned by the
firmware.

Set up PCI-E Memory Window registers using the true values programmed into
BAR registers.  When the PF4 "Master Function" is exported to a Virtual
Machine, the values returned by pci_resource_start() will be for the
synthetic PCI-E Configuration Space and not the real addresses. But we need
to program the PCI-E Memory Window address decoders with the real addresses
that we're going to be using in order to have accesses through the Memory
Windows work.

Based on origninal work by Casey Leedom <leedom@chelsio.com>
Signed-off-by: NCasey Leedom <leedom@chelsio.com>
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Change logic which determines our Physical Function at PCI Probe time.
Now we read the PL_WHOAMI register and get the Physical Function.

Pass Physical Function to Upper Layer Drivers in lld_info structure in the
new field "pf" added to lld_info.  This is useful for the cases where the
PF, say PF4, is attached to a Virtual Machine via some form of "PCI
Pass Through" technology and the PCI Function shows up as PF0 in the VM.

Based on original work by Casey Leedom <leedom@chelsio.com>
Signed-off-by: NCasey Leedom <leedom@chelsio.com>
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The ptp pin function programming does not allow calibration pin to change
function. This is problematic on hardware that uses the default calibration
pin for other purposes.

Removing this limitation does not impact calibration if userspace does not
reprogram the calibration pin.
Signed-off-by: NStefan Sørensen <stefan.sorensen@spectralink.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

For consistency, use the ptp_find_pin function to get the calibration pin,
not gpio_tab.
Signed-off-by: NStefan Sørensen <stefan.sorensen@spectralink.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This constraints the pin assignment to not allow the calibration function to
be reassigned and only allow reassigning the calibratin pin if only one phy is
connected.
Signed-off-by: NStefan Sørensen <stefan.sorensen@spectralink.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch increases the number of supported periodic output pins from
1 to 7. The last pin is reserved for sync.
Signed-off-by: NStefan Sørensen <stefan.sorensen@spectralink.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Periodic output triggers 0 and 1 of the dp83640 has a programmable
duty-cycle which is controlled by the Pulsewidth2 field of the trigger
data register.  This field is not documented in the datasheet, but it
is described in the "PHYTER Software Development Guide" section
3.1.4.1. Failing to set the field can result in unstable/no trigger
output.

Add programming of the Pulsewidth2 field, setting it to the same value
as the Pulsewidth field for a 50% duty cycle.
Signed-off-by: NStefan Sørensen <stefan.sorensen@spectralink.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

There are linux distributions where the inbox bnx2x driver contains SRIOV
support but doesn't contain the changes introduced in b9871bcf
"bnx2x: VF RSS support - PF side".

A VF in a VM running that distribution over a new hypervisor will access
incorrect addresses when trying to transmit packets, causing an attention
in the hypervisor and making that VF inactive until FLRed.

The driver in the VM has to ne upgraded [no real way to overcome this], but
due to the HW attention currently arising upgrading the driver in the VM
would not suffice [since the VF needs also be FLRed if the previous driver
was already loaded].

This patch causes the PF to fail the acquire message from a VF running an
old problematic driver; The VF will then gracefully fail it's probe preventing
the HW attention [and allow clean upgrade of driver in VM].
Signed-off-by: NYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: NAriel Elior <Ariel.Elior@qlogic.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This improves the performance of driver on machine with L1_CACHE_SHIFT of at
most 32 bytes [HW was planned for 64-byte aligned fastpath data].
Signed-off-by: NDmitry Kravkov <Dmitry.Kravkov@qlogic.com>
Signed-off-by: NYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: NAriel Elior <Ariel.Elior@qlogic.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Until now VFs were oblvious to the actual configured link parameters.
This patch does 2 things:

  1. It enables a PF to inform its VF using the bulletin board of the link
     configured, and allows the VF to present that information.

  2. It adds support of `ndo_set_vf_link_state', allowing the hypervisor
     to set the VF link state.
Signed-off-by: NDmitry Kravkov <Dmitry.Kravkov@qlogic.com>
Signed-off-by: NYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: NAriel Elior <Ariel.Elior@qlogic.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The PPS signal is not correct, as it generates a one half HZ clock
signal, as it only generates one level change per second. To generate a
full clock, we need two level changes per second. Also, change the name
of the #define, in order to prevent confusion between it and
NSEC_PER_SEC which is not guaranteed to be a 64bit value.
Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
Tested-by: NPhil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Call igb_setup_link() when the PHY is powered up.
Signed-off-by: NTodd Fujinaka <todd.fujinaka@intel.com>
Reported-by: NJeff Westfahl <jeff.westfahl@ni.com>
Tested-by: NAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Bump versions.

Change-ID: Id5082d7c3995fbddd22b3e303d804c86fcd240a3
Signed-off-by: NCatherine Sullivan <catherine.sullivan@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Add a slash to the branding string to reduce confusion and match up with
our other marketing materials.

Change-ID: I8229e8c3e43083b7a29c859a250f8d2d4dc46b9e
Signed-off-by: NMitch Williams <mitch.a.williams@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

We don't need the export.h header so we can just go ahead and remove it.

Change-ID: I9057396b141ee449d8299409081358b9270a7c4d
Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Prevent writing to reserved bits, queue index is 0-127

Change-ID: Ic923e1c92012a265983414acd8f547c4bdac2e34
Signed-off-by: NChristopher Pau <christopher.pau@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Driver needs to initialize all members of context descriptor. Stale
data is possible otherwise.

Change-ID: Idc6b53af45583509da42d5ec0824cbaf78aee64f
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

With the auto_disable flags added there was a bug that was causing the
replay logic to not work correctly.
This patch fixes the issue so that we call a replay after a sideband
reset correctly.

Change-ID: I005fe1ac361188ee5b19517a83c922038cba1b00
Signed-off-by: NAnjali Singhai Jain <anjali.singhai@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Add new variable defining ASQ command write back timeout to allow for
dynamic modification of this timeout. Initialize it on AQ initialize
routine with default value, vary it on device ID.

Change-ID: I5c9908f9d7c5455634353b694a986d6f146d1b9d
Signed-off-by: NKamil Krawczyk <kamil.krawczyk@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

In some circumstances, the firmware could beat us to the punch, and the
reply from the PF would come back before we were able to properly modify
the aq_pending and aq_required flags. This would mess up the flags and
put the driver in an indeterminate state, much like Schrödinger's cat.
However, unlike the cat, the driver is definitely dead.

To fix this, simply set the flags before sending the request to the AQ.
This way, it won't matter if the interrupt comes back too soon.

Change-ID: I9784655e475675ebcb3140cc7f36f4a96aaadce5
Signed-off-by: NMitch Williams <mitch.a.williams@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Make mask value of all 1s.  Value of -1 can't be used for u32 type.

Change-ID: I49d58b77639939fe7447a229dbf1f4a1bf7419ce
Signed-off-by: NKevin Scott <kevin.c.scott@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Per a recent HW designer comment, this code is for ripping through the
queues and interrupts to fully disable them on driver init, specifically
to help clean up after a PXE or other early boot activity.

Change-ID: I32ed452021a1c2b06dace1969976f882a37b9741
Signed-off-by: NShannon Nelson <shannon.nelson@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Clear the AQ BAH and BAL registers on a clean shutdown to help make sure
all is tidy when the driver is done.

Change-ID: I393e92680247daa52a8e00bab183213672d73578
Signed-off-by: NShannon Nelson <shannon.nelson@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Add the Base Address High and Low to the admin queue struct to simplify
another bit of "which context" logic in the config routines.

Change-ID: Iae195a7da3baffc1a9d522119e1e2b427068ad07
Signed-off-by: NShannon Nelson <shannon.nelson@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Checkpatch issued a warning preferring to use kstrto<type> when
using a single variable sscanf.  Change the sscanf invocation to
a kstrtouint call.
Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Currently the driver makes use of the additional mac address
registers in the hardware to provide perfect filtering.  The
hardware can also have a set of hash table registers that can
be used for imperfect filtering.  By using imperfect filtering
the additional mac address registers can be used for layer 2
filtering support.  Use the hash table registers if the device
has them.
Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds support for (imperfect) filtering of
VLAN tag ids using a 16-bit filter hash table.  When
VLANs are added, a 4-bit hash is calculated with the
result indicating the bit in the hash table to set.
This table is used by the hardware to drop packets with
a VLAN id that does not hash to a set bit in the table.
Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When receiving a VLAN packet check to be sure that VLAN
RX CTAG stripping is enabled before indicating that the
tag has been stripped in the packet information data
structure.
Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The MAC_VLAN_Incl register (0x0060) must be set to indicate
that the VLAN tag to be inserted comes from a Tx context
descriptor and not the MAC_VLAN_Incl register.  Also, even
though it is the default, explicitly set the type of tag to
be inserted as a CTAG.
Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

In order to avoid conflicts with other include files, add
a prefix to the defines in xgbe.h.
Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

There were a couple of fields in the fdir descriptor setup that
were not being reprogrammed, which left the opportunity for stale
data to be pushed as part of the descriptor next time it was used.

Change-ID: Ieee5c96a7d4713d469693f086c4854de949a7633
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

"fd current cnt" can be used to print the total filters consumed
by this interface, this includes guaranteed and best effort filters.

Change-ID: I2c417810c4999ce1388d2ea26f8e69679ba33966
Signed-off-by: NAnjali Singhai Jain <anjali.singhai@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Hardware does not have a way of telling a PF how much of the global
shared FD table space is still available or is consumed.
Previously, every PF but PF0 would think there was still space available
when there wasn't. The PFs would continue to try to add filters and fail.
With this new logic if a filter programming error is detected we just
check if we are close to the guaranteed space full and that can be used
as a hint to say, there might not be space and we should turn off the
features. This way we can turn off the feature in SW for all PFs in
time.

Change-ID: I725cb2fab16c033f883056362b4542c1400503c5
Signed-off-by: NAnjali Singhai Jain <anjali.singhai@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

There wasn't a need to play the logic twice, it seems
like a left over from when we had to add two PTYPEs for
one filter. There should be no change in the number of
filters that actually got added to the hardware.

Change-ID: I5071d02eafd020b60e30eb96219f110f334eec85
Signed-off-by: NAnjali Singhai Jain <anjali.singhai@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Currently every time we run through the i40e_ptp_init routine, we create
a new device node. This function is called by i40e_reset_and_rebuild
which is used to handle reset of the device. Even though the 1588
registers only get cleared on a GLOBAL reset, this function is still
called to handle a CORE reset.

This causes a leak of PTP device nodes at every reset. To fix this,
break PTP device clock node creation out of i40e_ptp_init, and only call
this if we don't already have a device created. Further invocation of
i40e_ptp_init will not generate new PTP devices. Instead, only the
necessary work required to reconfigure 1588 will be done.

This change also fixes an issue where a reset can cause the
device to forget it's timestamp configuration, and revert to the default
mode.

Change-ID: I741d01c61d9fe1d24887859d1316e1a8a892909e
Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

This patch prevents the SIOCGHWTSTAMP ioctl from possibly returning bad
data, by not permanently storing the setting into the private
structure until after we've finished validating that we can support it.

Change-ID: Ib59f9b4f73f451d5a2e76fb8efa5d4271b218433
Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>