1. 08 5月, 2013 5 次提交
  2. 20 3月, 2013 2 次提交
  3. 19 2月, 2013 1 次提交
  4. 01 2月, 2013 1 次提交
  5. 13 12月, 2012 1 次提交
  6. 09 11月, 2012 4 次提交
  7. 06 10月, 2012 1 次提交
  8. 01 10月, 2012 1 次提交
    • J
      MIPS: BCM63XX: Properly handle mac address octet overflow · d21a7713
      Jonas Gorski 提交于
      While calculating the mac address the pointer for the current octet was
      never reset back to the least significant one after being decremented
      because of an octet overflow. This resulted in the code continuing to
      increment at the current octet, potentially generating duplicate or
      invalid mac addresses.
      
      As a second issue the pointer was allowed to advance up to the most
      significant octet, modifying the OUI, and potentially changing the type
      of mac address.
      
      Rewrite the code so it resets the pointer to the least significant
      in each outer loop step, and bails out when the least significant octet
      of the OUI is reached.
      Signed-off-by: NJonas Gorski <jonas.gorski@gmail.com>
      Cc: linux-mips@linux-mips.org
      Cc: Maxime Bizon <mbizon@freebox.fr>
      Cc: Florian Fainelli <florian@openwrt.org>
      Cc: Sergei Shtylyov <sshtylyov@mvista.com>
      Patchwork: https://patchwork.linux-mips.org/patch/4348/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      d21a7713
  9. 31 8月, 2012 2 次提交
  10. 25 8月, 2012 3 次提交
  11. 17 8月, 2012 1 次提交
    • F
      MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348. · 5a670445
      Florian Fainelli 提交于
      BCM6338 and BCM6348 have a message control register width of 8 bits, instead
      of 16-bits like what the SPI driver assumes right now. Also the SPI message
      type shift value of 14 is actually 6 for these SoCs.
      This resulted in transmit FIFO corruption because we were writing 16-bits
      to an 8-bits wide register, thus spanning on the first byte of the transmit
      FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo().
      
      Fix this by passing the message control register width and message type
      shift through platform data back to the SPI driver so that it can use
      it properly.
      Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
      Cc: linux-mips@linux-mips.org
      Cc: grant.likely@secretlab.ca
      Cc: spi-devel-general@lists.sourceforge.net
      Cc: jonas.gorski@gmail.com
      Patchwork: https://patchwork.linux-mips.org/patch/3983/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5a670445
  12. 24 7月, 2012 9 次提交
  13. 23 7月, 2012 4 次提交
  14. 19 7月, 2012 1 次提交
  15. 21 5月, 2012 1 次提交
  16. 06 2月, 2012 1 次提交
  17. 10 1月, 2012 1 次提交
  18. 08 12月, 2011 1 次提交