ENDXFER polling is available on version 3.10a and later of the
DWC_usb3 (USB 3.0) controller. With this feature, the software can poll
the CMDACT bit in the DEPCMD register after issuing an ENDXFER command.
This feature is enabled by writing GUCTL2[14].

This feature is NOT available on the DWC_usb31 (USB 3.1) IP.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

When dwc3 core enters into suspend mode, the system (especially for mobile
device) may power off the dwc3 controller for power saving, that will cause
dwc3 controller lost the mode operation when resuming dwc3 core.

Thus we can move the mode setting into dwc3_core_init() function to avoid this
issue.
Signed-off-by: NBaolin Wang <baolin.wang@linaro.org>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: NWilliam Wu <william.wu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Support to configure the UTMI+ PHY with an 8- or 16-bit
interface via DT. The UTMI+ PHY interface is a hardware
capability, and it's platform dependent. Normally, the
PHYIF can be configured during coreconsultant.

But for some specific USB cores(e.g. rk3399 SoC DWC3),
the default PHYIF configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: NWilliam Wu <william.wu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: NWilliam Wu <william.wu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Implementations might use different IRQs for
host, gadget so use named interrupt resources
to allow device tree to specify the interrupts.

Following are the interrupt names

Peripheral Interrupt - peripheral
HOST Interrupt - host

Maintain backward compatibility for a single named
interrupt ("dwc3_usb3") for all interrupts as well as
unnamed interrupt at index 0 for all interrupts.

As platform_get_irq() variants are used, tackle
the -EPROBE_DEFER case as well.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

If there is a failure after pm_runtime_enable/get_sync()
we need to call pm_runtime_disable/put_sync().

Otherwise it will lead to an unbalanced pm_runtime_enable() on the
subsequent probe if the earlier probe bailed out due to -EPROBE_DEFER.

pm_runtime_get_sync() can fail as well so deal with that case too.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

We shouldn't change a host-only dwc3 to gadget-only
if driver is built as gadget-only. Fix that up here.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

No more users for it.
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

this patch implements the most basic pm_runtime
support for dwc3. Whenever USB cable is dettached,
then we will allow core to runtime_suspend.

Runtime suspending will involve completely tearing
down event buffers and require a full soft-reset of
the IP.

Note that a further optimization could be
implemented once we decide to support hibernation,
which is to allow runtime_suspend with cable
connected when bus is in U3. That's subject to a
separate patch, however.
Tested-by: NBaolin Wang <baolin.wang@linaro.org>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

now that we have re-factored dwc3_core_init() and
dwc3_core_exit() we can use them for suspend/resume
operations.

This will help us avoid some common mistakes when
patching code when we have duplicated pieces of code
doing the same thing.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

The idea of this patch is for dwc3_core_init() to
abstract all the details about how to initialize
dwc3 and dwc3_core_exit() to do the same for
teardown.

With this, we can simplify suspend/resume operations
by a large margin and always know that we're going
to start dwc3 from a known starting point.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

this patch is in preparation for some further
re-factoring in dwc3 initialization. No functional
changes.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

that macro is unnecessary and just adds pointless
obfuscation. Let's remove it.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

this helper will be used, initially, to dump space
of different queues and fifos in dwc3 to
debugfs. Later, it'll be used to issue remote wakeup
when we want to start a transfer and there's
something in a TX FIFO.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Debugfs init failure is not so important. We can continue our job on
this failure. Also no break need for debugfs_create_file call failure.
Signed-off-by: NDu, Changbin <changbin.du@intel.com>

[felipe.balbi@linux.intel.com :
	- remove out-of-memory message, we get that from OOM.
	- switch dev_err() to dev_dbg() ]
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Some freescale QorIQ platforms require to disable receiver detection
in P3 for correct detection of USB devices. If GUSB3PIPECTL(DISRXDETINP3)
is set, Core will change PHY power state to P2 and then perform receiver
detection. After receiver detection, Core will change PHY power state to
P3. Same quirk would be added in dts file in future patches.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

we need to power off the PHY during suspend and
power it back on during resume.
Signed-off-by: NFelipe Balbi <balbi@kernel.org>
[nsekhar@ti.com: fix call to usb_phy_set_suspend() in dwc3_suspend()]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

we will be using a single event buffer and that
renders ev_buffs array unnecessary. Let's remove it
in favor of a single pointer to a single event
buffer.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

We never, ever route any of the other event buffers
so we might as well drop support for them.

Until someone has a real, proper benefit for
multiple event buffers, we will rely on a single
one. This also helps reduce memory footprint of
dwc3.ko which won't allocate memory for the extra
event buffers.
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

That FIFO resizing logic was added to support OMAP5
ES1.0 which had a bogus default FIFO size. I can't
remember the exact size of default FIFO, but it was
less than one bulk superspeed packet (<1024) which
would prevent USB3 from ever working on OMAP5 ES1.0.

However, OMAP5 ES1.0 support has been dropped by
commit aa2f4b16 ("ARM: OMAP5: id: Remove ES1.0
support") which renders FIFO resizing unnecessary.
Tested-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

According to Synopsys Databook, we shouldn't be
relying on GCTL.CORESOFTRESET bit as that's only for
debugging purposes. Instead, let's use DCTL.CSFTRST
if we're OTG or PERIPHERAL mode.

Host side block will be reset by XHCI driver if
necessary. Note that this reduces amount of time
spent on dwc3_probe() by a long margin.

We're still gonna wait for reset to finish for a
long time (default to 1ms max), but tests show that
the reset polling loop executed at most 19 times
(modprobe dwc3 && modprobe -r dwc3 executed 1000
times in a row).
Suggested-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Check that dwc->maximum_speed is set to a valid value. Also add an error
when we use it later if we encounter an invalid value.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@kernel.org>

If the maximum_speed is not set, set it to a known value, either
SuperSpeed or SuperSpeedPlus based on the type of controller we are
using. If we are on DWC_usb31 controller, check the PHY interface to see
if it is capable of SuperSpeedPlus.

Also this check is moved after dwc3_core_init() so that we can check
dwc->revision.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@kernel.org>

The last few dev_dbg() messages are converted to
tracepoints and we can finally ignore dev_dbg()
messages during debug sessions.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.

Cc: <stable@vger.kernel.org> # v3.18+
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch allows the dwc3 driver to run on the new Synopsys USB 3.1
IP core, albeit in USB 3.0 mode only.

The Synopsys USB 3.1 IP (DWC_usb31) retains mostly the same register
interface and programming model as the existing USB 3.0 controller IP
(DWC_usb3). However the GSNPSID and version numbers are different.

Add checking for the new ID to pass driver probe.

Also, since the DWC_usb31 version number is lower in value than the
full GSNPSID of the DWC_usb3 IP, we set the high bit to identify
DWC_usb31 and to ensure the values are higher.

Finally, add a documentation note about the revision numbering scheme.
Any future revision checks (for STARS, workarounds, and new features)
should take into consideration how it applies to both the 3.1/3.0 IP.

Cc: <stable@vger.kernel.org> # v3.18+
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

No functional affect on existing platforms, but the driver
is now ready to extract the properties also from ACPI tables
as well as from DT.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

By using the unified device property interface, the function
can be made available for all platforms and not just the
ones using DT.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

By using the unified device property interface, the function
can be made available for all platforms and not just the
ones using DT.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Add support for USB DRVVBUS pinctrl state change during
suspend/resume. This helps is conserving power during
system sleep.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Add adjust_frame_length_quirk for writing to fladj register
which adjusts (micro)frame length to value provided by
"snps,quirk-frame-length-adjustment" property thus avoiding
USB 2.0 devices to time-out over a longer run
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

When a SoC supports both PHY interfaces but
doesn't define HSPHY in DT/pdata, we will get
an unnecessary dev_warn() which can mislead users
into thinking that they're missing something.

Instead, let's just silently rely on a correct
default. If the HW default is wrong, then HSPHY
is required and USB won't work, this will be
motivation enough for engineers to patch their
way into a working setup.
Reported-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

commit 3e10a2ce ("usb: dwc3: add hsphy_interface
property") introduced a possible NULL pointer
dereference because dwc->hsphy_interface can be
NULL.

In order to fix it, all we have to do is guard
strncmp() against a NULL argument.

Fixes: 3e10a2ce ("usb: dwc3: add hsphy_interface property")
Tested-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Registers DWC3's ULPI interface with the ULPI bus when it's
available.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Platforms that have configured DWC_USB3_HSPHY_INTERFACE with
value 3, i.e. UTMI+ and ULPI, need to inform the driver of
the actual HSPHY interface type with the property. "utmi" if
the interface is UTMI+ or "ulpi" if the interface is ULPI.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This allows dwc3_phy_setup() to be more useful later. There
is nothing preventing the PHY configuration registers from
being programmed early. They do not loose their context in
soft reset.

There are however other PHY related operations that should
be executed before the driver request handles to the PHYs,
such as registering DWC3's ULPI interface, which can now be
done in dwc3_phy_setup().

Also, if there ever was need for the two 100ms delays in
dwc3_phy_setup() there isn't anymore. The PHYs are now reset
after the PHY interfaces are setup.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

So it can be called from other places later.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

So they are available when ULPI interface support is added.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

We need to store it before phys are handled, so we can later
use it in ULPI interface support code.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>