- 27 1月, 2018 7 次提交
-
-
由 Benjamin Herrenschmidt 提交于
The USB port 1 clock gate control has an inversed polarity from all the other clock gates in the chip. This makes the aspeed_clk_{enable,disable} functions honor the flag CLK_GATE_SET_TO_DISABLE and set that flag appropriately so it's set for all clocks except USB port 1. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Wei Yongjun 提交于
In case of error, the function of_iomap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: a2e230c7b2ea ("clk: Add clock driver for ASPEED BMC SoCs") Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Joel Stanley 提交于
There are some resets that are not associated with gates. These are represented by a reset controller. Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Signed-off-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Joel Stanley 提交于
The majority of the clocks in the system are gates paired with a reset controller that holds the IP in reset. This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: 1. Place IP in reset 2. Enable clock 3. Delay 4. Release reset There are some gates that do not have an associated reset; these are handled by using -1 as the index for the reset. Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Signed-off-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Joel Stanley 提交于
This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Signed-off-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Joel Stanley 提交于
This registers the core clocks; those which are required to calculate the rate of the timer peripheral so the system can load a clocksource driver. Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Signed-off-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Joel Stanley 提交于
This adds the stub of a driver for the ASPEED SoCs. The clocks are defined and the static registration is set up. Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Signed-off-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 19 1月, 2018 5 次提交
-
-
由 Paul Cercueil 提交于
Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Signed-off-by: NMaarten ter Huurne <maarten@treewalker.org> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/Signed-off-by: NJames Hogan <jhogan@kernel.org>
-
由 Paul Cercueil 提交于
This commit permits the PLLs to be dynamically enabled and disabled when their children clocks are enabled and disabled. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18480/Signed-off-by: NJames Hogan <jhogan@kernel.org>
-
由 Paul Cercueil 提交于
The second PLL of the JZ4770 does not have a bypass bit. This commit makes it possible to support it with the current common CGU code. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18479/Signed-off-by: NJames Hogan <jhogan@kernel.org>
-
由 Paul Cercueil 提交于
Previously, the clocks with a fixed divider would report their rate as being the same as the one of their parent, independently of the divider in use. This commit fixes this behaviour. This went unnoticed as neither the jz4740 nor the jz4780 CGU code have clocks with fixed dividers yet. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18477/Signed-off-by: NJames Hogan <jhogan@kernel.org>
-
由 Paul Cercueil 提交于
The CGU common code does not modify the pointed clk_ops structure, so it should be marked as const. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18476/Signed-off-by: NJames Hogan <jhogan@kernel.org>
-
- 11 1月, 2018 6 次提交
-
-
由 Sean Wang 提交于
Changes from v1->v2: Add 'select RESET_CONTROLLER' under COMMON_CLK_MEDIATEK and enable reset.c to be built when COMMON_CLK_MEDIATEK is selected. That should be quite reasonable because the reset controller is tightly embedded inside and exported from these clock subsystems. At least it can be found on infracfg and pericfg subsystem that both are really fundamental block lots of devices must depend on. commit 74cb0d6d ("clk: mediatek: fixup test-building of MediaTek clock drivers") can let the build system looking into the directory where the clock drivers resides and then allow test-building the drivers. But the change also gives rise to certain incorrect behavior which is reset.c being built even not depending on either COMPILE_TEST or ARCH_MEDIATEK alternative dependency. To get rid of reset.c being built unexpectedly on the other platforms, it would be a good change that the file should be built depending on its own specific configuration rather than just on generic RESET_CONTROLLER one. Signed-off-by: NSean Wang <sean.wang@mediatek.com> Cc: Jean Delvare <jdelvare@suse.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 David Lechner 提交于
Reentrant calls to clk_enable() are not working on UP systems. This is caused by the fact spin_trylock_irqsave() always returns true when CONFIG_SMP=n (and CONFIG_DEBUG_SPINLOCK=n) which causes the reference counting to not work correctly when clk_enable_lock() is called twice before clk_enable_unlock() is called (this happens when clk_enable() is called from within another clk_enable()). This fixes the problem by skipping the call to spin_trylock_irqsave() on UP systems and relying solely on reference counting. We also make sure to set flags in this case so that we are not returning an uninitialized value. Suggested-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NDavid Lechner <david@lechnology.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 weiyongjun (A) 提交于
platform_get_resource() may return NULL, add proper check to avoid potential NULL dereferencing. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Stephen Boyd 提交于
We don't need a goto here. Drop it. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Geert Uytterhoeven 提交于
When exposing data access through debugfs, the correct debugfs_create_*() functions must be used, matching the data types. Remove all casts from data pointers passed to debugfs_create_*() functions, as such casts prevent the compiler from flagging bugs. clk_core.rate and .accuracy are "unsigned long", hence casting their addresses to "u32 *" exposed the wrong halves on big-endian 64-bit systems. Fix this by using debugfs_create_ulong() instead. Octal permissions are preferred, as they are easier to read than symbolic permissions. Hence replace "S_IRUGO" by "0444" throughout. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> [sboyd@codeaurora.org: Squash the octal change in too] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Geert Uytterhoeven 提交于
Currently the virtual "clk_flags" file in debugfs shows the numeric value of the top-level framework flags for the specified clock. Hence the user must manually interpret these values. Moreover, on big-endian 64-bit systems, the wrong half of the value is shown, due to the cast from "unsigned long *" to "u32 *". Fix both issues by showing the symbolic flag names instead. Any non-standard flags are shown as a hex number. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 05 1月, 2018 3 次提交
-
-
由 ABE Hiroshige 提交于
This patch adds FDP1-0 clock to the R8A7796 SoC. Signed-off-by: NABE Hiroshige <hiroshige.abe.zc@renesas.com> Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> [geert: s/fdp0/fdp1-0/] Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
-
由 Stephen Boyd 提交于
We can move these APIs into the private header file now that we don't have any users of the __clk_get() and __clk_put() APIs outside of clkdev.c and clk.c. Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Stephen Boyd 提交于
We'd like to privatize __clk_get(), but the sunxi clk driver is calling this function to keep a reference held on the clk and call clk_prepare_enable() on it. We support this design in the clk core now with the CLK_IS_CRITICAL flag, so let's just use that instead. Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 04 1月, 2018 1 次提交
-
-
由 Geert Uytterhoeven 提交于
The "flags" parameter passed to of_clk_detect_critical() cannot be a pointer to a real clk_core.flags field, as clk_core is private to the clock framework internals. Change the comment to refer to top-level framework flags instead. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 03 1月, 2018 5 次提交
-
-
由 Jernej Škrabec 提交于
TCON1 also has M divider, contrary to TCON0. And the mux is only 2 bits wide, instead of 3. Fixes: 05359be1 ("clk: sunxi-ng: Add driver for A83T CCU") Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> [wens@csie.org: Add description about mux width difference] Signed-off-by: NChen-Yu Tsai <wens@csie.org>
-
由 Stephen Boyd 提交于
Now that all the users of asm/clkdev.h have been replaced with the generic file we can get rid of the asm-generic file as well and implement that code directly where it's used. We only have one caller of __clkdev_alloc(), in clkdev.c so we can easily remove that and drop the include of asm/clkdev.h in linux/clkdev.h by putting the __clk_get/__clk_put inlines in their respective location. Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Georgi Djakov 提交于
Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org> Tested-by: NAmit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Include rcg header for parent_map, drop multiple unneeded includes, add COMPILE_TEST to APCS depends, made tristate/modular] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Georgi Djakov 提交于
Add support for hardware that can switch both parent clock and divider at the same time. This avoids generating intermediate frequencies from either the old parent clock and new divider or new parent clock and old divider combinations. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Tested-by: NAmit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Change a comment style, drop parent_map in favor of a u32 array instead, export symbols for clk_ops and mux function] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Georgi Djakov 提交于
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org> Tested-by: NAmit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Move to devm provider registration, NUL terminate frequency table, made tristate/modular] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 29 12月, 2017 12 次提交
-
-
由 Icenowy Zheng 提交于
The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3 DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE module clock). Fix this by change the clock descriptions to use the clocks of H3. Fixes: 763c5bd0 ("clk: sunxi-ng: add support for DE2 CCU") Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Signed-off-by: NChen-Yu Tsai <wens@csie.org>
-
由 Icenowy Zheng 提交于
Allwinner H3 features a DE2 CCU like the one on A83T, however the parent of the clocks is the DE module clock, not the PLL_DE clock. Add support for it. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Signed-off-by: NChen-Yu Tsai <wens@csie.org>
-
由 Jerome Brunet 提交于
divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider' At the following line: > div = _get_div(table, val, flags, divider->width); in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider' Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before Fixes: afe76c8f ("clk: allow a clk divider with max divisor when zero") Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Gomonovych, Vasyl 提交于
Fix ptr_ret.cocci warnings: drivers/clk/mvebu/armada-37xx-periph.c:362:1-3: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Signed-off-by: NVasyl Gomonovych <gomonovych@gmail.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Lori Hikichi 提交于
There were a few fields in the iproc pll data structures that were holding information that was not true state information. Using stack variables is sufficient and simplifies the structure. There are not any functional changes in this commit. Signed-off-by: NLori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Lori Hikichi 提交于
The iproc plls are capable of doing small rate changes without the need for a full reset and re-lock procedure. This feature will allow for small tweaks to the PLL rate to occur smoothly. Signed-off-by: NLori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Lori Hikichi 提交于
The pll post divider code was using DIV_ROUND_UP when determining the divider value best suited to produce the target frequency. Using DIV_ROUND_CLOSEST will give us better divider values when the division results in a small remainder. Also, change the post divider clock over to the determine_rate api instead of round_rate. Signed-off-by: NSimran Rai <ssimran@broadcom.com> Signed-off-by: NLori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Lori Hikichi 提交于
Add the ability for the iproc pll to calculate the pll parameters at runtime instead of only using predefined tables. This ability allows the clock users to select from the full range of vco frequencies. The old method of table based programming is retained so that existing users will retain expected behavior. The flag IPROC_CLK_PLL_CALC_PARAM will need to be set to enable the new runtime calculation method. Currently, this is only being enabled for the audio pll. This feature also revealed a problem with the driver using the round_rate api. The round_rate api does not allow for frequencies larger than 2^31 to be returned. Those large frequencies are interpreted as an error code. Therefore, we are moving to the determine_rate api which solves this problem. Signed-off-by: NSimran Rai <ssimran@broadcom.com> Signed-off-by: NLori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Wu Fengguang 提交于
Fixes: b26ff127 ("clk: si5351: Apply PLL soft reset before enabling the outputs") Signed-off-by: NFengguang Wu <fengguang.wu@intel.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Igor Grinberg 提交于
Since switching to clk drivers, the CLK_POUT cannot be searched for by clk_get() API and thus it returns with ENOENT. Register it with the clk_lookup and thus unbreak the users of it. Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 weiyongjun (A) 提交于
Fixes the following sparse warning: drivers/clk/meson/axg.c:260:25: warning: symbol 'axg_gp0_params_table' was not declared. Should it be static? Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 weiyongjun (A) 提交于
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 78b4af31 ("clk: meson-axg: add clock controller drivers") Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 27 12月, 2017 1 次提交
-
-
由 Dong Aisheng 提交于
Current clk_pm_runtime_put is using pm_runtime_put_sync which is not safe to be called in clk_core_is_enabled as it should be able to run in atomic context. Thus use pm_runtime_put instead which is atomic safe. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Fixes: 9a34b453 ("clk: Add support for runtime PM") Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com> Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-