1. 16 11月, 2017 12 次提交
  2. 11 11月, 2017 1 次提交
  3. 05 10月, 2017 1 次提交
  4. 13 9月, 2017 1 次提交
  5. 08 9月, 2017 3 次提交
    • F
      drm/i915/gvt: Refine error handling in dispatch_workload · 0f43702a
      fred gao 提交于
      When an error occurs in dispatch_workload, this patch is to do the
      proper cleanup and rollback to the original states before the workload
      is abandoned.
      
      v2:
      - split the mixed several error paths for better review. (Zhenyu)
      
      v3:
      - original PTR_ERR(cs) is good and code cleanup. (Zhenyu)
      
      v4:
      - reuse the existing i915_add_request for error handling. (Zhenyu)
      
      v5:
      - remove the duplicate error handling release_shadow_wa_ctx and
        move the engine->context_unpin upper. (Zhenyu)
      
      v6:
      - keep the old label "out". (Zhenyu)
      Signed-off-by: Nfred gao <fred.gao@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      0f43702a
    • F
      drm/i915/gvt: Add error handling for intel_gvt_scan_and_shadow_workload · a3cfdca9
      fred gao 提交于
      When an error occurs after shadow_indirect_ctx, this patch is to do the
      proper cleanup and rollback to the original states for shadowed indirect
      context before the workload is abandoned.
      
      v2:
      - split the mixed several error paths for better review. (Zhenyu)
      
      v3:
      - no return check for clean up functions. (Changbin)
      
      v4:
      - expose and reuse the existing release_shadow_wa_ctx. (Zhenyu)
      
      v5:
      - move the release function to scheduler.c file. (Zhenyu)
      
      v6:
      - move error handling code of intel_gvt_scan_and_shadow_workload
        to here. (Zhenyu)
      Signed-off-by: Nfred gao <fred.gao@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      a3cfdca9
    • F
      drm/i915/gvt: Separate cmd scan from request allocation · 0a53bc07
      fred gao 提交于
      Currently i915 request structure and shadow ring buffer are allocated
      before command scan, so it will have to restore to previous states once
      any error happens afterwards in the long dispatch_workload path.
      
      This patch is to introduce a reserved ring buffer created at the beginning
      of vGPU initialization. Workload will be coped to this reserved buffer and
      be scanned first, the i915 request and shadow ring buffer are only
      allocated after the result of scan is successful.
      
      To balance the memory usage and buffer alloc time, the coming bigger ring
      buffer will be reallocated and kept until more bigger buffer is coming.
      
      v2:
      - use kmalloc for the smaller ring buffer, realloc if required. (Zhenyu)
      
      v3:
      - remove the dynamically allocated ring buffer. (Zhenyu)
      
      v4:
      - code style polish.
      - kfree previous allocated buffer once kmalloc failed. (Zhenyu)
      Signed-off-by: Nfred gao <fred.gao@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      0a53bc07
  6. 10 8月, 2017 4 次提交
  7. 02 8月, 2017 1 次提交
  8. 11 7月, 2017 2 次提交
  9. 21 6月, 2017 1 次提交
  10. 08 6月, 2017 2 次提交
    • P
      drm/i915/gvt: Trigger scheduling after context complete · f100daec
      Ping Gao 提交于
      The time based scheduler poll context busy status at every
      micro-second during vGPU switch, it will make GPU idle for a while
      when the context is very small and completed before the next
      micro-second arrival. Trigger scheduling immediately after context
      complete will eliminate GPU idle and improve performance.
      
      Create two vGPU with same type, run Heaven simultaneously:
      Before this patch:
       +---------+----------+----------+
       |         |  vGPU1   |   vGPU2  |
       +---------+----------+----------+
       |  Heaven |  357     |    354   |
       +-------------------------------+
      
      After this patch:
       +---------+----------+----------+
       |         |  vGPU1   |   vGPU2  |
       +---------+----------+----------+
       |  Heaven |  397     |    398   |
       +-------------------------------+
      
      v2: Let need_reschedule protect by gvt-lock.
      Signed-off-by: NPing Gao <ping.a.gao@intel.com>
      Signed-off-by: NWeinan Li <weinan.z.li@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      f100daec
    • C
      drm/i915/gvt: implement per-vm mmio switching optimization · 0e86cc9c
      Changbin Du 提交于
      Commit ab9da627906a ("drm/i915: make context status notifier head be
      per engine") gives us a chance to inspect every single request. Then
      we can eliminate unnecessary mmio switching for same vGPU. We only
      need mmio switching for different VMs (including host).
      
      This patch introduced a new general API intel_gvt_switch_mmio() to
      replace the old intel_gvt_load/restore_render_mmio(). This function
      can be further optimized for vGPU to vGPU switching.
      
      To support individual ring switch, we track the owner who occupy
      each ring. When another VM or host request a ring we do the mmio
      context switching. Otherwise no need to switch the ring.
      
      This optimization is very useful if only one guest has plenty of
      workloads and the host is mostly idle. The best case is no mmio
      switching will happen.
      
      v2:
        o fix missing ring switch issue. (chuanxiao)
        o support individual ring switch.
      Signed-off-by: NChangbin Du <changbin.du@intel.com>
      Reviewed-by: NChuanxiao Dong <chuanxiao.dong@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      0e86cc9c
  11. 04 5月, 2017 1 次提交
  12. 28 4月, 2017 1 次提交
    • J
      drm/i915: Sanitize engine context sizes · 63ffbcda
      Joonas Lahtinen 提交于
      Pre-calculate engine context size based on engine class and device
      generation and store it in the engine instance.
      
      v2:
      - Squash and get rid of hw_context_size (Chris)
      
      v3:
      - Move after MMIO init for probing on Gen7 and 8 (Chris)
      - Retained rounding (Tvrtko)
      v4:
      - Rebase for deferred legacy context allocation
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Oscar Mateo <oscar.mateo@intel.com>
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Cc: intel-gvt-dev@lists.freedesktop.org
      Acked-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      63ffbcda
  13. 13 4月, 2017 1 次提交
  14. 29 3月, 2017 1 次提交
  15. 22 3月, 2017 1 次提交
    • C
      drm/i915/gvt: Use force single submit flag to distinguish gvt request from i915 request · bc2d4b62
      Changbin Du 提交于
      In my previous Commit ab9da627906a ("drm/i915: make context status
      notifier head be per engine") rely on scheduler->current_workload[x]
      to distinguish gvt spacial request from i915 request. But this is
      not always true since no synchronization between workload_thread and
      lrc irq handler.
      
          lrc irq handler               workload_thread
               ----                          ----
        pick i915 requests;
                                      intel_vgpu_submit_execlist();
                                      current_workload[x] = xxx;
        shadow_context_status_change();
      
      Then current_workload[x] is not null but current request is of i915 self.
      So instead we check ctx flag CONTEXT_FORCE_SINGLE_SUBMISSION. Only gvt
      request set this flag and always set.
      
      v2: Reverse the order of multi-condition 'if' statement.
      
      Fixes: ab9da6279 ("drm/i915: make context status notifier head be per engine")
      Signed-off-by: NChangbin Du <changbin.du@intel.com>
      Reviewed-by: NYulei Zhang <yulei.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      bc2d4b62
  16. 21 3月, 2017 1 次提交
  17. 17 3月, 2017 6 次提交