ARM: AM33XX: Fix configuration of dmtimer parent clock by dmtimer driverDate:Wed, 17 Oct 2012 13:55:55 -0500

Add dmtimer clock aliases for AM33XX devices so that the parent clock for
the dmtimer can be set correctly by the dmtimer driver. Without these clock
aliases the dmtimer driver will fail to find the parent clocks for the dmtimer.

Verified that DMTIMERs can be successfully requested on AM335x beagle bone.

Original patch was provided by Vaibhav Hiremath [1]. Changelog and
additional verification performed by Jon Hunter.

[1] http://marc.info/?l=linux-omap&m=134693631608018&w=2Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
Tested-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

After Rajendra's common-clock preparation series,
commit (a1978ef4da1 - ARM: omap: hwmod: get rid of
all omap_clk_get_by_name usage) the clkdev table need to
update with an entry for clocks used by hwmod to have
clock name same as the alias.

Without this, the clk_get() in omap_hwmod would fail.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add AM335x cpu0 clock entry to the corresponding clock data file. This
is useful in getting the correct mpu clock pointer to change the cpu
frequency in cpufreq driver.
Signed-off-by: NAnilKumar Ch <anilkumar@ti.com>
[paul@pwsan.com: changed patch subject]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

These can now be moved to be local headers in mach-omap2.

Note that this patch removes arch/arm/plat-omap/devices.c as it
will get removed anyways with Paul Walmsley's patch
"ARM: OMAP: split OMAP1, OMAP2+ RNG device registration".
Signed-off-by: NTony Lindgren <tony@atomide.com>

Currently, the device names for the dcan module follows the
format "dcan.X", where 'X' is the dcan instance number.
On other side, driver may request for clock with/without con_id
and dev_id, and it is expected that platform should respect this
request and return the requested clock handle.

Now, when using device tree, the format of the device name created
by OF layer is different, "<reg-address>.<device-name>",
assuming that the device-tree "reg" property is specified.
This causes the look-up failure for clock node in dcan driver

To fix this add new dcan clock alias for using device-tree.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

With commit ae6df418
Sub: ARM: OMAP2+: dmtimer: cleanup fclk usage)
The Timer functional clock naming convention has changed from
gptX_fck => timerXfck, and so as the timer init function
in mach-omap2/timer.c.
OMAP4 clocktree also has changed accordingly.

AM33xx Clock Tree has been merged during rc3-4 timeframe,
before above commit got merged, so similar change is required
for AM33xx as well (Change the gptX_fck => timerX_fck).
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

AM33XX clock implementation is different than any existing OMAP
family of devices. Although DPLL module is similar to OMAP4
device, but the usage is very much different than OMAP4.
AM33XX has different peripheral set and each module gets
integrated to the clock framework differently than OMAP
family of devices.

This patch adds full Clock tree data for AM33XX family
of devices and also integrates it into existing OMAP framework.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NVaibhav Bedia <vaibhav.bedia@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
CC: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: updated to apply; changed 'soc_is_am33xx' to
 'cpu_is_am33xx' to match usage in Tony's current am33xx branch]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>