Add New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
Signed-off-by: NFabien Lahoudere <fabien.lahoudere@collabora.co.uk>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The AUO T215HVN01 is a 21.5" FHD (1920x1080) color TFT LCD panel.

This panel is used on the Acer Chromebase 21.5-inch All-in-One (DC221HQ).

Link to spec: http://www.udmgroup.com/ftp/T215HVN01.0.pdf

v2: fix alphabetical order
v3: remove minor revision suffix ".0" and add link to spec
v4: add dt-binding documentation
Signed-off-by: NHaixia Shi <hshi@chromium.org>
Tested-by: NHaixia Shi <hshi@chromium.org>
Reviewed-by: NStéphane Marchesin <marcheu@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Sharp 15" LQ150X1LG11 panel is an XGA TFT LCD panel.

The simple-panel driver is used to get support for essential
functionality of the panel.
Signed-off-by: NGustaf Lindström <gl@axentia.se>
Signed-off-by: NPeter Rosin <peda@axentia.se>
[treding@nvidia.com: change .bpc from 8 to 6]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The format is RGB888 not RGB666.
Signed-off-by: NJonathan Liu <net147@gmail.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Taking our cue from commit a42f6e3f ("drm/panel: simple: Add delay
timing for Sharp LQ123P1JX31"), let's add timings:

 .prepare = t1 + t3
 .enable = t7
 .unprepare = t11 + 12

Without this, the panel may not be given enough time to come up.
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This display expects DE pin and data lines to be active high, add the
necessary flags.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Thierry Reding <treding@nvidia.com>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch adds support for Innolux Corporation 10.1" G101ICE-L01 WXGA
(1280x800) LVDS panel to the simple-panel driver.
Signed-off-by: NMichael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

According to page 16 of the Sharp LQ123P1JX31 datasheet, we need to add
the missing delay timing. Panel prepare time should be t1 (0.5 to 10 ms)
plus t3 (0 to 100 ms), panel enable time should equal to t7 (0 to 50 ms)
and panel unprepare time should be t11 (1 to 50 ms) plus t12 (500 ms).
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Reviewed-by: NSean Paul <seanpaul@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.

EDID shows:
  Detailed mode: Clock 147.000 MHz, 263 mm x 164 mm
                 1920 1936 1952 1984 hborder 0
                 1200 1215 1217 1235 vborder 0
                 -hsync -vsync
  Manufacturer-specified data, tag 15
  ASCII string: STARRY
  ASCII string: KR122EA0SRA
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add simple-panel support for the  Sharp LQ101K1LY04, which  is a 10"
WXGA (1280x800) LVDS panel.
Signed-off-by: NJoshua Clayton <stillcompiling@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Sharp LQ123P1JX31 is an 12.3", 2400x1600 TFT-LCD panel connected
using eDP interfaces.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel
connected using eDP interfaces.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Some backlight drivers ignore the power property and instead only use
the state property. Fixup the panel driver to set the state property in
addition to the power property.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This blank line was introduced in commit c8521969 ("drm/panel:
simple: Add support for BOE TV080WUM-NL0"), likely by mistake.
Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Both the Innolux ZJ070NA-01P and Samsung LTN101NT05 were listing the
horizontal and vertical resolutions in the size.width and size.height
fields, whereas they should contain the physical dimensions of the
panel.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for TPK U.S.A. LLC Fusion 7", 10.1" panels to the DRM simple
panel driver.
Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for the Innolux AT070TN92 panel.
Signed-off-by: NRiccardo Bortolato <bortolato@navaltechitalia.it>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

drm_display_mode_from_videomode() already calls drm_mode_set_name() on
the provided mode.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
[treding@nvidia.com: slightly reword commit message]
Signed-off-by: NThierry Reding <treding@nvidia.com>

All modes exposed by simple panels should be tagged as driver defined
modes. Moreover, if a panel supports only one mode, this mode is
obviously the preferred one.

Doing this also fix a problem occurring when a 'video=' parameter is
passed on the kernel command line. In some cases the user provided mode
will be preferred over the simple panel ones, which might result in
unpredictable behavior.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: NNicolas Ferre <nicolas.ferre@atmel.com>
[treding@nvidia.com: reshuffle some code for consistency]
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
panel driver.

It is a 480x272 panel connected through a 24-bits RGB interface.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This is a basic TFT panel with a 40-pin FPC connector on it.  The
specification doesn't define timings, but the Adafruit instructions
were setting up 800x480 CVT.

v2: Add .bus_format and vsync/hsync flags.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NRob Herring <robh@kernel.org>
[treding@nvidia.com: keep entries properly sorted]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The drivers current default configuration drives the pixel data
on rising edge of the pixel clock. However, most display sample
data on rising edge... This leads to color shift artefacts visible
especially at edges.

This patch changes the relevant defines to be useful and actually
set the bits, and changes pixel clock polarity to drive the pixel
data on falling edge by default. The patch also adds an explicit
pixel clock polarity flag to the display introduced with the driver
(NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to
retain the initial behavior.
Signed-off-by: NStefan Agner <stefan@agner.ch>

Introduce bus_flags to specify display bus properties like signal
polarities. This is useful for parallel display buses, e.g. to
specify the pixel clock or data enable polarity.
Suggested-by: NThierry Reding <thierry.reding@gmail.com>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NManfred Schlaegl <manfred.schlaegl@gmx.at>
Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NStefan Agner <stefan@agner.ch>

Add support for United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT
LCD panels in the simple-panel driver.
Signed-off-by: NMaciej S. Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The LG lp120up1 TFT LCD panel with eDP interface is a 12.0" 1920x1280
panel, which can be supported by the simple panel driver.
Signed-off-by: NJitao Shi <jitao.shi@mediatek.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Set hsync/vsync to active low for g121x1_l03 panel to match the
recommended setting in the datasheet.
Signed-off-by: NAkshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The current default configuration is as follows:
- Invert VSYNC signal (active LOW)
- Invert HSYNC signal (active LOW)

The mode flags allow to specify the required polarity per
mode. Furthermore, none of the current driver settings is
actually a standard polarity.

This patch applies the current driver default polarities as
explicit flags to the display which has been introduced with
the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now
also parses the flags field and applies the configuration
accordingly, by using the following values as standard
polarities: (e.g. when no flags are specified):
- VSYNC signal not inverted (active HIGH)
- HSYNC signal not inverted (active HIGH)
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>

The QiaoDian Xianshi QD43003C0-40 is a 4"3 TFT LCD panel.

Timings from the OTA5180A document, ver 0.9, section
10.1.1:
  http://www.orientdisplay.com/pdf/OTA5180A.pdfSigned-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Document that 'width' and 'height' are measured in millimeters.
Signed-off-by: NUlrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Kyocera TCG121XGLP panel is an XGA LCD TFT panel connected through
LVDS, which can be supported by the simple panel driver.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for Innolux CheMei 12" G121X1-L03 XGA LVDS display.

Datasheet: http://www.azdisplays.com/PDF/G121X1-L03.pdfSigned-off-by: NAkshay Bhat <akshay.bhat@timesys.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel
connected using four DSI lanes. It can be supported by the simple-panel
driver.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for the Okaya RS800480T-7X0GP to the DRM simple panel
driver.

The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel
LCD interface. It supports pixel clocks in the range of 30-40 MHz.

This panel details can be found at:
http://boundarydevices.com/product/7-800x480-display/Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM
simple panel driver.
Signed-off-by: NAlison Wang <b18965@freescale.com>
Signed-off-by: NXiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: NJianwei Wang <jianwei.wang.chn@gmail.com>
Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
[treding@nvidia.com: add .bpc field for panel]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The AUO B080UAN01 is an 8.0" WUXGA TFT LCD panel connected using four
DSI lanes. It can be supported by the simple-panel driver.
Signed-off-by: NThierry Reding <treding@nvidia.com>

According to the data sheet, the minimum horizontal blanking interval
is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
minimum working horizontal blanking interval to be 60 clocks.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The bus format both specifies the bpc and the way the individual bits get
serialized into the 7 LVDS timeslots.

While the is only one standard mapping for 6 bpc and so the driver could
infer the bit mapping from the bpc alone, there are more options for the
8 bpc case which makes specifiying the bus format mandatory.
To keep things consistent across panels and to set a precedent for new
panel additions add the proper bus format.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch adds the bus_format field to the HSD100PXN1 panel structure.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>