- 26 10月, 2019 2 次提交
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由 Evan Quan 提交于
For Arcturus, clock limit settings on uclk/socclk/fclk domains are not supported. V2: simplify the code to support both SGPU and MGPU cases Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
This is a quick and low risk fix. Those APIs which are exposed to other IPs or to support sysfs/hwmon interfaces or DAL will have lock protection. Meanwhile no lock protection is enforced for swSMU internal used APIs. Future optimization is needed. V2: strip the lock protection for all swSMU internal APIs Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: NFeifei Xu <Feifei.Xu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 03 10月, 2019 2 次提交
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由 Alex Deucher 提交于
Fix DOC link name, clean up formatting in pp_dpm_* section. Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Adam Zerella 提交于
Some of the documentation formatting could be improved which will resolve some Sphinx amdgpu build warnings e.g WARNING: Unexpected indentation. WARNING: Block quote ends without a blank line; unexpected unindent. WARNING: Inline emphasis start-string without end-string. Signed-off-by: NAdam Zerella <adam.zerella@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 8月, 2019 1 次提交
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由 Jean Delvare 提交于
The driver does not support these sensors yet and there is no point in creating sysfs attributes which will always return an error. Signed-off-by: NJean Delvare <jdelvare@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 8月, 2019 1 次提交
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由 Evan Quan 提交于
Do not expose those unsupported clock domains through sysfs on Arcturus. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NKevin Wang <kevin1.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 7月, 2019 7 次提交
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由 Evan Quan 提交于
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NKenneth Feng <kenneth.feng@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
DPM state relates are not supported on the new SW SMU ASICs. But still it's not OK to trigger null pointer dereference on accessing them. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NKenneth Feng <kenneth.feng@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Kevin Wang 提交于
1. Unified feature enable status format in sysfs 2. Rename ppfeature to pp_features to adapt other pp sysfs node name 3. this function support all asic, not asic related function. Signed-off-by: NKevin Wang <kevin1.wang@amd.com> Reviewed-by: NKenneth Feng <kenneth.feng@amd.com> Acked-by: NRui Huang <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
DPM state relates are not supported on the new SW SMU ASICs. But still it's not OK to trigger null pointer dereference on accessing them. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Add checking for possible invalid input and null pointer. And drop redundant code. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Drop redundant check, duplicate check, duplicate setting and fix the return value. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 7月, 2019 2 次提交
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由 Alex Deucher 提交于
On vega20, there is an SMU message to query it. On navi, it's fetched from the metrics table. Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
On vega20, there is an SMU message to query it. On navi, it's fetched from the metrics table. Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 7月, 2019 1 次提交
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由 Alex Deucher 提交于
The dpm sensor function already does this for us. This fixes the freq*_input files with the new SMU implementation. Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 18 7月, 2019 1 次提交
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由 Evan Quan 提交于
As the lock was already held on the entrance to smu_handle_task. - V2: lock in small granularity Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NKevin Wang <kevin1.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 28 6月, 2019 1 次提交
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由 Evan Quan 提交于
Make mem_busy_percent sysfs interface invisible on Vega10. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 26 6月, 2019 2 次提交
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由 Ernst Sjöstrand 提交于
Reported by smatch: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1496 amdgpu_hwmon_show_temp() error: uninitialized symbol 'temp'. Signed-off-by: NErnst Sjöstrand <ernstp@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Ernst Sjöstrand 提交于
Reported by smatch: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:693 amdgpu_set_pp_od_clk_voltage() error: uninitialized symbol 'ret'. Signed-off-by: NErnst Sjöstrand <ernstp@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 6月, 2019 3 次提交
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由 Kevin Wang 提交于
the smu->mutex is internal lock resource in sw-smu, some functions will use it at the same time, so it maybe will cause deadlock issue. this patch fix this issue in smu_force_performance_level function. Signed-off-by: NKevin Wang <kevin1.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Kevin Wang 提交于
add sysfs interface of force_clk_levels sysfs for navi10. Signed-off-by: NKevin Wang <kevin1.wang@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Kevin Wang 提交于
add sysfs interface of print_clk_levels sysfs for navi10. Signed-off-by: NKevin Wang <kevin1.wang@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 21 6月, 2019 2 次提交
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由 Jack Xiao 提交于
Enable athub2 clock gating and light sleep Signed-off-by: NJack Xiao <Jack.Xiao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jack Zhang 提交于
Tonga sriov need to use smu to load firmware. Remove sriov flag because the default return value is zero. Signed-off-by: NJack Zhang <Jack.Zhang1@amd.com> Reviewed-by: NTrigger Huang <Trigger.Huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 14 6月, 2019 2 次提交
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由 Alex Deucher 提交于
Fixes SI cards running on amdgpu. Fixes: 19290598 ("drm/amd/amdgpu: add RLC firmware to support raven1 refresh") Bug: https://bugs.freedesktop.org/show_bug.cgi?id=110883Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yintian Tao 提交于
we need register pm sysfs for virt in order to support dpm level modification because smu ip block will not be added under SRIOV v2: whitespace fixes (Alex) Signed-off-by: NYintian Tao <yttao@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 13 6月, 2019 1 次提交
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由 Alex Deucher 提交于
Fixes SI cards running on amdgpu. Fixes: 19290598 ("drm/amd/amdgpu: add RLC firmware to support raven1 refresh") Bug: https://bugs.freedesktop.org/show_bug.cgi?id=110883Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 12 6月, 2019 2 次提交
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由 Trigger Huang 提交于
For SR-IOV VF, powerplay may not be supported, in this case, error '-EINVAL' should not be returned. Signed-off-by: NTrigger Huang <Trigger.Huang@amd.com> Reviewed-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Use SMU firmware version to indentify the raven1 refresh device and then load homologous RLC FW. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Suggested-by: Huang Rui<Ray.Huang@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 11 6月, 2019 1 次提交
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由 Sam Ravnborg 提交于
Drop use of drmP.h in all files named amdgpu* in drm/amd/amdgpu/ Fix fallout. Signed-off-by: NSam Ravnborg <sam@ravnborg.org> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-10-sam@ravnborg.org
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- 06 6月, 2019 1 次提交
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由 Prike Liang 提交于
Use SMU firmware version to indentify the raven1 refresh device and then load homologous RLC FW. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Suggested-by: Huang Rui<Ray.Huang@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 25 5月, 2019 8 次提交
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由 Kent Russell 提交于
Add a file that provides a Unique ID for the GPU. This will persist across machines and is guaranteed to be unique. This is only available for GFX9 and newer, so older ASICs will not have this file in the sysfs pool v2: Store it in adev for ASICs that don't have a hwmgr Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NKent Russell <kent.russell@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Support ppfeatures sysfs interface on Vega20 sw smu routine. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tom St Denis 提交于
Signed-off-by: NTom St Denis <tom.stdenis@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
A new sysfs interface mem_busy_percent is added for telling how busy the VRAM is(in percentage). Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Expose temp[1-3]_label hwmon interfaces. While temp2_label and temp3_label are visible for SOC15 dGPUs only. - V2: correct temp1_label as "edge" Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Two new hwmon interfaces(temp2_input and temp3_input) are added. They are supported on SOC15 dGPUs only. - V2: correct thermal sensor output Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
These new interfaces(temp1_emergency, temp2_emergency, temp3_emergency) are supported on SOC15 dGPUs only. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
These new interfaces(temp2_crit, temp2_crit_hyst, temp3_crit, temp3_crit_hyst) are supported on SOC15 dGPUs only. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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