Allwinner reworked the PLL4 clock in sun7i; so we need to change the
compatible. Additionally, PLL8 is compatible with this new PLL4
implementation, so let's add a node for it as well.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: NCarlo Caione <carlo@caione.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: mark.rutland@arm.com
Cc: hdegoede@redhat.com
Acked-by: maxime.ripard@free-electrons.com
Link: http://lkml.kernel.org/r/1395256879-8475-3-git-send-email-carlo@caione.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The watchdog compatibles were following a different pattern than the one found
in the other devices. Now that the driver supports the right pattern, switch to
it in the DT.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Switch the device tree to the new compatibles introduced in the timer driver
to have a common pattern accross all Allwinner SoCs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
Signed-off-by: NRoman Byshko <rbyshko@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This patch adds sunxi sata support to A20 boards that have such a connector.
Some boards also feature a regulator via a GPIO and support for this is also
added.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A20 has 4 SPI controllers compatible with the one found in the A10. Add
them in the DT.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Switch the device tree to the new compatibles introduced in the clock drivers
to have a common pattern accross all Allwinner SoCs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A20 SoC is built around a pair of Cortex-A7 cores,
which have the usual generic timers. Report this in the DT.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: NRoman Byshko <rbyshko@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

All Allwinner A20 boards we support can only use either EMAC or GMAC,
as they share the same pins. As we have switched all supported to
GMAC, we should alias GMAC (the active controller) as ethernet0,
so u-boot will insert the MAC address for the correct controller.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A20 has EMAC and GMAC muxed on the same pins.
Add pin sets with gmac function for MII and RGMII mode to the DTSI.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Switch the device tree touchscreen compatibles to have a common pattern accross
all Allwinner SoCs. Since the touchscreen driver has not been merged yet, it
has no side effect.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A20 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A20 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.

Fix this for the remaining DT nodes that slipped through.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Cc: stable@vger.kernel.org

Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Switch the device tree to the new compatibles introduced in the ethernet and
mdio drivers to have a common pattern accross all Allwinner SoCs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

UART2 is used on CubieTruck to connect to the Bluetooth module.
Add the pin set used in this case.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some UART aliases have been defined, but not all of them. Add the remaining
ones to be consistent and to ease the parsing of the DT by the bootloaders.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Device tree naming conventions state that node names should match
the nodes function. Change external low speed oscillator node name
to match.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This patch adds the clock output pin options on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

mbus is the memory bus clock, and it is present on both sun5i and sun7i
machines. Its register layout is compatible with the mod0 one.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This commit adds all the mod0 clocks available on A20 to its device
tree. This list was created by looking at AW's code release.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
device trees.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
device trees. PLL4 is compatible with PLL1.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A20 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A20 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org #3.12+
Signed-off-by: NOlof Johansson <olof@lixom.net>

The Allwinner A20 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the
device tree.

[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

U-Boot uses the ethernet0 alias to locate the right node to fill in
the MAC address of the first ethernet interface. This patch adds the
alias on all the sunxi SoCs with EMAC. In this way, people using
ethernet in U-Boot (eg, for tftp) can keep a consistent address on both
U-Boot and Linux with no additional effort.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add the RTC node to DTS for Allwinner A10 and Allwinner A20.
Signed-off-by: NCarlo Caione <carlo.caione@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A20 boards we currently have share the same pins for the i2c
controllers they share. Add them to the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A20 shares the same I2C controller than the one that could
be found on earlier SoCs from Allwinner. There is only a few more of
these controllers. Add all of them in the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This patch shall add support for the sunxi-sid driver to the device
tree for A10, A10s, A13 and A20.
Signed-off-by: NOliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A20 has several muxing options for the EMAC. Yet, the currently
supported boards only use one set of them. Add that pin set to the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The Allwinner A20 SoC also have the EMAC found on the A10 and A10s.
Enable the support for it in the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Now that the clock driver knows about the available clocks found on the
A20, we can build up the clock tree from the device tree.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The UARTs on the A20 can be muxed to several pins. Add a few options to
the DTSI so that we can start using them in the boards' DT.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>