1. 02 12月, 2020 1 次提交
  2. 27 10月, 2020 2 次提交
  3. 15 8月, 2020 1 次提交
  4. 19 12月, 2019 1 次提交
  5. 12 12月, 2019 1 次提交
    • Y
      drm/amd/powerplay: enable pp one vf mode for vega10 · c9ffa427
      Yintian Tao 提交于
      Originally, due to the restriction from PSP and SMU, VF has
      to send message to hypervisor driver to handle powerplay
      change which is complicated and redundant. Currently, SMU
      and PSP can support VF to directly handle powerplay
      change by itself. Therefore, the old code about the handshake
      between VF and PF to handle powerplay will be removed and VF
      will use new the registers below to handshake with SMU.
      mmMP1_SMN_C2PMSG_101: register to handle SMU message
      mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
      mmMP1_SMN_C2PMSG_103: register to handle SMU response
      
      v2: remove module parameter pp_one_vf
      v3: fix the parens
      v4: forbid vf to change smu feature
      v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
      v6: change skip condition at vega10_copy_table_to_smc
      Signed-off-by: NYintian Tao <yttao@amd.com>
      Acked-by: NEvan Quan <evan.quan@amd.com>
      Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      c9ffa427
  6. 23 11月, 2019 1 次提交
  7. 19 11月, 2019 1 次提交
  8. 01 7月, 2019 1 次提交
    • L
      drm/amdgpu: Don't skip display settings in hwmgr_resume() · 688f3d1e
      Lyude Paul 提交于
      I'm not entirely sure why this is, but for some reason:
      
      921935dc ("drm/amd/powerplay: enforce display related settings only on needed")
      
      Breaks runtime PM resume on the Radeon PRO WX 3100 (Lexa) in one the
      pre-production laptops I have. The issue manifests as the following
      messages in dmesg:
      
      [drm] UVD and UVD ENC initialized successfully.
      amdgpu 0000:3b:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring vce1 test failed (-110)
      [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <vce_v3_0> failed -110
      [drm:amdgpu_device_resume [amdgpu]] *ERROR* amdgpu_device_ip_resume failed (-110).
      
      And happens after about 6-10 runtime PM suspend/resume cycles (sometimes
      sooner, if you're lucky!). Unfortunately I can't seem to pin down
      precisely which part in psm_adjust_power_state_dynamic that is causing
      the issue, but not skipping the display setting setup seems to fix it.
      Hopefully if there is a better fix for this, this patch will spark
      discussion around it.
      
      Fixes: 921935dc ("drm/amd/powerplay: enforce display related settings only on needed")
      Cc: Evan Quan <evan.quan@amd.com>
      Cc: Alex Deucher <alexander.deucher@amd.com>
      Cc: Huang Rui <ray.huang@amd.com>
      Cc: Rex Zhu <Rex.Zhu@amd.com>
      Cc: Likun Gao <Likun.Gao@amd.com>
      Cc: <stable@vger.kernel.org> # v5.1+
      Signed-off-by: NLyude Paul <lyude@redhat.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      688f3d1e
  9. 28 6月, 2019 1 次提交
    • L
      drm/amdgpu: Don't skip display settings in hwmgr_resume() · ee006eb0
      Lyude Paul 提交于
      I'm not entirely sure why this is, but for some reason:
      
      921935dc ("drm/amd/powerplay: enforce display related settings only on needed")
      
      Breaks runtime PM resume on the Radeon PRO WX 3100 (Lexa) in one the
      pre-production laptops I have. The issue manifests as the following
      messages in dmesg:
      
      [drm] UVD and UVD ENC initialized successfully.
      amdgpu 0000:3b:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring vce1 test failed (-110)
      [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <vce_v3_0> failed -110
      [drm:amdgpu_device_resume [amdgpu]] *ERROR* amdgpu_device_ip_resume failed (-110).
      
      And happens after about 6-10 runtime PM suspend/resume cycles (sometimes
      sooner, if you're lucky!). Unfortunately I can't seem to pin down
      precisely which part in psm_adjust_power_state_dynamic that is causing
      the issue, but not skipping the display setting setup seems to fix it.
      Hopefully if there is a better fix for this, this patch will spark
      discussion around it.
      
      Fixes: 921935dc ("drm/amd/powerplay: enforce display related settings only on needed")
      Cc: Evan Quan <evan.quan@amd.com>
      Cc: Alex Deucher <alexander.deucher@amd.com>
      Cc: Huang Rui <ray.huang@amd.com>
      Cc: Rex Zhu <Rex.Zhu@amd.com>
      Cc: Likun Gao <Likun.Gao@amd.com>
      Cc: <stable@vger.kernel.org> # v5.1+
      Signed-off-by: NLyude Paul <lyude@redhat.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      ee006eb0
  10. 18 6月, 2019 1 次提交
  11. 12 6月, 2019 1 次提交
  12. 06 6月, 2019 1 次提交
  13. 26 1月, 2019 1 次提交
  14. 15 1月, 2019 1 次提交
  15. 03 1月, 2019 1 次提交
  16. 04 12月, 2018 1 次提交
  17. 11 10月, 2018 1 次提交
  18. 10 10月, 2018 1 次提交
  19. 14 9月, 2018 2 次提交
  20. 28 8月, 2018 1 次提交
    • E
      drm/amd/powerplay: add the hw manager for vega20 (v3) · da958630
      Evan Quan 提交于
      hwmgr is the interface for the driver to setup state
      structures which are used by the smu for managing the
      power state.
      
      v2: squash in fixes:
      - update set_watermarks_for_clocks_ranges to use common code
      - drop unsupported apis
      - correct MAX_REGULAR_DPM_NUMBER value
      - multimonitor fixes
      - add check for vbios pptable version
      - revise dpm table setup
      - init fclk dpm state
      - Remove unused definition in vega20_hwmgr
      - support power limit setup
      - enable vega20 to honour DAL clock limits
      - comment out dump_table debugging
      v3: switch to SOC15 register access macros
      Signed-off-by: NEvan Quan <evan.quan@amd.com>
      Reviewed-by: NHuang Rui <ray.huang@amd.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      da958630
  21. 14 7月, 2018 1 次提交
  22. 16 6月, 2018 1 次提交
  23. 15 6月, 2018 1 次提交
  24. 17 5月, 2018 1 次提交
  25. 16 5月, 2018 3 次提交
  26. 12 4月, 2018 2 次提交
  27. 22 3月, 2018 4 次提交
  28. 15 3月, 2018 4 次提交
  29. 08 3月, 2018 1 次提交