The rest of the code refers to version 1.2 of the MIPI D-PHY
specification. But this comment refers to 2.1, while a sub comment of
the function refers to 1.2 again. Replace 2.1 with 1.2.
Signed-off-by: NSebastian Fricke <sebastian.fricke@posteo.net>
Link: https://lore.kernel.org/r/20210421041740.8451-1-sebastian.fricke@posteo.netSigned-off-by: NVinod Koul <vkoul@kernel.org>

For a single PHY, there's no reason to have a phy-names entry in DT.
The DT specific get functions allow for this already, but devm_phy_get()
WARNs in this case. Other subsystems also don't warn in their get
functions. Let's drop the WARN for DT case in devm_phy_get().

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Signed-off-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210414135525.3535787-1-robh@kernel.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Based on code from downstream Codeaurora tree. The ipq60xx has one gen3
PCIe port.
Signed-off-by: NSelvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Link: https://lore.kernel.org/r/e24f2bedb8a7346018b58136bcb0a4004d8677a0.1620203062.git.baruch@tkos.co.ilSigned-off-by: NVinod Koul <vkoul@kernel.org>

The way of printing the pointer address for the 'port_base'
address got into compile warnings on some architectures
[-Wpointer-to-int-cast]. Instead of use '%08x' and cast
to an 'unsigned int' just make use of '%px' and avoid the
cast. To avoid not really needed driver verbosity on normal
behaviour change also from 'dev_info' to 'dev_dbg'.

Fixes: d87da323 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-7-sergio.paracuellos@gmail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Make dependent on PCI_MT7621 configuration option and mark
this pci phy configuration as bool which has more sense.
Signed-off-by: NSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-6-sergio.paracuellos@gmail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

After use the clock apis and avoid custom architecture
code this driver can properly be enabled for COMPILE_TEST.
Signed-off-by: NSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-5-sergio.paracuellos@gmail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

MT7621 SoC clock driver has already mainlined in
'commit 48df7a26 ("clk: ralink: add clock driver for mt7621 SoC")'
This allow us to properly use kernel clock apis to get
the clock frequency needed for the phy configuration
instead of use custom architecture code to do the same.
Signed-off-by: NSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-4-sergio.paracuellos@gmail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

This reverts commit 00f2e6f6 ("phy: ti: j721e-wiz: add missing of_node_put")
as it erroneously adds the of_node_put() as incorrect place.
Reported-by: NJunlin Yang <yangjunlin@yulong.com>
Link: https://lore.kernel.org/r/20210408062914.3813102-1-vkoul@kernel.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

When compiling with CONFIG_PHY_J721E_WIZ, Hulk Robot reported:

drivers/phy/ti/phy-j721e-wiz.c: In function ‘wiz_mux_clk_register’:
drivers/phy/ti/phy-j721e-wiz.c:659:17: error: implicit declaration of function ‘kzalloc’; did you mean ‘vzalloc’? [-Werror=implicit-function-declaration]
  659 |  parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
      |                 ^~~~~~~
      |                 vzalloc
drivers/phy/ti/phy-j721e-wiz.c:659:15: warning: assignment to ‘const char **’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion]
  659 |  parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
      |               ^
drivers/phy/ti/phy-j721e-wiz.c:697:2: error: implicit declaration of function ‘kfree’; did you mean ‘vfree’? [-Werror=implicit-function-declaration]
  697 |  kfree(parent_names);
      |  ^~~~~
      |  vfre

Fixes: 040cbe76 ("phy: ti: j721e-wiz: Model the internal clocks without device tree input")
Reported-by: NHulk Robot <hulkci@huawei.com>
Signed-off-by: NShixin Liu <liushixin2@huawei.com>
Link: https://lore.kernel.org/r/20210408012829.432938-1-liushixin2@huawei.comSigned-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This driver's remove path calls cancel_delayed_work(). However, that
function does not wait until the work function finishes. This means
that the callback function may still be running after the driver's
remove function has finished, which would result in a use-after-free.

Fix by calling cancel_delayed_work_sync(), which ensures that
the work is properly cancelled, no longer running, and unable
to re-schedule itself.
Reported-by: NHulk Robot <hulkci@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20210407092716.3270248-1-yangyingliang@huawei.comSigned-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

We have currently three users of the PSEC_PER_SEC each of them defining it
individually. Instead, move it to time64.h to be available for everyone.

There is a new user coming with the same constant in use. It will also
make its life easier.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

drivers/phy/microchip/sparx5_serdes.c:2440:54-57: ERROR: Missing resource_size with iores

 Use resource_size function on resource object
 instead of explicit computation.

Generated by: scripts/coccinelle/api/resource_size.cocci

Fixes: 2ff8a1ee ("phy: Add Sparx5 ethernet serdes PHY driver")
CC: Steen Hegelund <steen.hegelund@microchip.com>
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: Nkernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20210318232844.GA65886@63b0c5462fdaSigned-off-by: NVinod Koul <vkoul@kernel.org>

Use direct register operations instead of a table of register
information to lower the stack usage.
Signed-off-by: NSteen Hegelund <steen.hegelund@microchip.com>
Reported-by: Nkernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20210329141309.612459-2-steen.hegelund@microchip.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

s/Hisilicon/HiSilicon/g.
It should use capital S, according to the official website.
Signed-off-by: NHao Fang <fanghao11@huawei.com>
Link: https://lore.kernel.org/r/1617278537-26102-1-git-send-email-fanghao11@huawei.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

When USB and USB_COMMON are not enabled, phy-mvebu-cp110-utmi
suffers a build error due to a missing interface that is provided
by CONFIG_USB_COMMON, so make the driver depend on USB_COMMON.

ld: drivers/phy/marvell/phy-mvebu-cp110-utmi.o: in function `mvebu_cp110_utmi_phy_probe':
phy-mvebu-cp110-utmi.c:(.text+0x152): undefined reference to `of_usb_get_dr_mode_by_phy'
Signed-off-by: NRandy Dunlap <rdunlap@infradead.org>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: linux-phy@lists.infradead.org
Link: https://lore.kernel.org/r/20210401210045.23525-1-rdunlap@infradead.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform).
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-6-dmitry.baryshkov@linaro.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-5-dmitry.baryshkov@linaro.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

In preparation to adding support for V4 DP PHY move DP functions to
callbacks at struct qmp_phy_cfg.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-4-dmitry.baryshkov@linaro.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Configure 'p_standard_mode' only for DP/QSGMII as for other modes
it's not used as per the programming sequence. Add "continue" in the
else to prevent random value from being written to p_standard_mode.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210331131417.15596-1-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

The current driver is not handling the clock enable/disable operations
properly. The clocks need to be handled correctly by enabling or
disabling at appropriate places. This patch adds code to handle the
same.
Signed-off-by: NManish Narani <manish.narani@xilinx.com>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/1616588325-95602-1-git-send-email-manish.narani@xilinx.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

The Microchip Sparx5 SerDes PHY is present only Microchip Sparx5 SoCs.
Hence add a dependency on ARCH_SPARX5, to prevent asking the user about
this driver when configuring a kernel without support for Sparx5 SoCs.

Fixes: 2ff8a1ee ("phy: Add Sparx5 ethernet serdes PHY driver")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210331081937.367408-1-geert+renesas@glider.beSigned-off-by: NVinod Koul <vkoul@kernel.org>

The Torrent spec specifies delay of 660.5us after phy_reset is
asserted by the controller. To be on the safe side provide a delay
of 5ms to 10ms in ->phy_on() callback where the SERDES is already
configured in bootloader.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210330110138.24356-6-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. Since the reset controls obtained in
Torrent is exclusively used by the Torrent device, use
exclusive reset control request API calls.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-5-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Do not configure torrent SERDES if it's already configured.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-4-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change intended. Group reset APIs and clock APIs in
preparation for adding support to skip configuration if the SERDES
is already configured by bootloader.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-3-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Serdes lanes might be shared between multiple cores in some usecases
and its not possible to lock PLLs for both the lanes independently
by the two cores. This requires a bootloader to configure both the
lanes at early boot time.

To handle this case, skip all configuration if any of the lanes has
already been enabled.
Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210330110138.24356-2-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-14-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

commit 44d30d62 ("phy: cadence: Add driver for Sierra PHY") enabled
the clock in probe and failed to disable in remove callback. Add missing
clk_disable_unprepare() in cdns_sierra_phy_remove().

Fixes: 44d30d62 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210319124128.13308-11-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-10-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Acked-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-8-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-7-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-6-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

"serdes" node (child node of WIZ) can have sub-nodes for representing links
or it can have sub-nodes for representing the various clocks within the
serdes. Instead of trying to read "reg" from every child node used for
assigning "lane_phy_type", read only if the child node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" subnode.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210319124128.13308-5-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-4-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Invoke wiz_init() before configuring anything else in Sierra/Torrent
(invoked as part of of_platform_device_create()). wiz_init() resets the
SERDES device and any configuration done in the probe() of
Sierra/Torrent will be lost. In order to prevent SERDES configuration
from getting reset, invoke wiz_init() immediately before invoking
of_platform_device_create().

Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Cc: <stable@vger.kernel.org> # v5.10
Link: https://lore.kernel.org/r/20210319124128.13308-3-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Commit 44d30d62 ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.

Fixes: 44d30d62 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Cc: <stable@vger.kernel.org> # v5.4+
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add hbr3_hbr2 voltage and premphasis swing table to support
HBR3 link rate.
Signed-off-by: NKuogee Hsieh <khsieh@codeaurora.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1615914761-12300-1-git-send-email-khsieh@codeaurora.org
Fixes: 52e013d0 ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy")
Signed-off-by: NVinod Koul <vkoul@kernel.org>

Fix the return value check typo which testing the wrong variable
in ingenic_usb_phy_probe().

Fixes: 31de313d ("PHY: Ingenic: Add USB PHY driver using generic PHY framework.")
Reported-by: NHulk Robot <hulkci@huawei.com>
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Acked-by: NPaul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210305034933.3240914-1-weiyongjun1@huawei.comSigned-off-by: NVinod Koul <vkoul@kernel.org>