1. 09 8月, 2021 1 次提交
    • V
      net: dsa: centralize fast ageing when address learning is turned off · 045c45d1
      Vladimir Oltean 提交于
      Currently DSA leaves it down to device drivers to fast age the FDB on a
      port when address learning is disabled on it. There are 2 reasons for
      doing that in the first place:
      
      - when address learning is disabled by user space, through
        IFLA_BRPORT_LEARNING or the brport_attr_learning sysfs, what user
        space typically wants to achieve is to operate in a mode with no
        dynamic FDB entry on that port. But if the port is already up, some
        addresses might have been already learned on it, and it seems silly to
        wait for 5 minutes for them to expire until something useful can be
        done.
      
      - when a port leaves a bridge and becomes standalone, DSA turns off
        address learning on it. This also has the nice side effect of flushing
        the dynamically learned bridge FDB entries on it, which is a good idea
        because standalone ports should not have bridge FDB entries on them.
      
      We let drivers manage fast ageing under this condition because if DSA
      were to do it, it would need to track each port's learning state, and
      act upon the transition, which it currently doesn't.
      
      But there are 2 reasons why doing it is better after all:
      
      - drivers might get it wrong and not do it (see b53_port_set_learning)
      
      - we would like to flush the dynamic entries from the software bridge
        too, and letting drivers do that would be another pain point
      
      So track the port learning state and trigger a fast age process
      automatically within DSA.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      045c45d1
  2. 08 8月, 2021 1 次提交
  3. 07 8月, 2021 5 次提交
  4. 06 8月, 2021 9 次提交
  5. 05 8月, 2021 24 次提交
    • P
      net: vxge: fix use-after-free in vxge_device_unregister · 942e560a
      Pavel Skripkin 提交于
      Smatch says:
      drivers/net/ethernet/neterion/vxge/vxge-main.c:3518 vxge_device_unregister() error: Using vdev after free_{netdev,candev}(dev);
      drivers/net/ethernet/neterion/vxge/vxge-main.c:3518 vxge_device_unregister() error: Using vdev after free_{netdev,candev}(dev);
      drivers/net/ethernet/neterion/vxge/vxge-main.c:3520 vxge_device_unregister() error: Using vdev after free_{netdev,candev}(dev);
      drivers/net/ethernet/neterion/vxge/vxge-main.c:3520 vxge_device_unregister() error: Using vdev after free_{netdev,candev}(dev);
      
      Since vdev pointer is netdev private data accessing it after free_netdev()
      call can cause use-after-free bug. Fix it by moving free_netdev() call at
      the end of the function
      
      Fixes: 6cca2003 ("vxge: cleanup probe error paths")
      Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
      Signed-off-by: NPavel Skripkin <paskripkin@gmail.com>
      Reviewed-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      942e560a
    • P
      net: fec: fix use-after-free in fec_drv_remove · 44712965
      Pavel Skripkin 提交于
      Smatch says:
      	drivers/net/ethernet/freescale/fec_main.c:3994 fec_drv_remove() error: Using fep after free_{netdev,candev}(ndev);
      	drivers/net/ethernet/freescale/fec_main.c:3995 fec_drv_remove() error: Using fep after free_{netdev,candev}(ndev);
      
      Since fep pointer is netdev private data, accessing it after free_netdev()
      call can cause use-after-free bug. Fix it by moving free_netdev() call at
      the end of the function
      Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
      Fixes: a31eda65 ("net: fec: fix clock count mis-match")
      Signed-off-by: NPavel Skripkin <paskripkin@gmail.com>
      Reviewed-by: NJoakim Zhang <qiangqing.zhang@nxp.com>
      Reviewed-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      44712965
    • P
      net: pegasus: fix uninit-value in get_interrupt_interval · af35fc37
      Pavel Skripkin 提交于
      Syzbot reported uninit value pegasus_probe(). The problem was in missing
      error handling.
      
      get_interrupt_interval() internally calls read_eprom_word() which can
      fail in some cases. For example: failed to receive usb control message.
      These cases should be handled to prevent uninit value bug, since
      read_eprom_word() will not initialize passed stack variable in case of
      internal failure.
      
      Fail log:
      
      BUG: KMSAN: uninit-value in get_interrupt_interval drivers/net/usb/pegasus.c:746 [inline]
      BUG: KMSAN: uninit-value in pegasus_probe+0x10e7/0x4080 drivers/net/usb/pegasus.c:1152
      CPU: 1 PID: 825 Comm: kworker/1:1 Not tainted 5.12.0-rc6-syzkaller #0
      ...
      Workqueue: usb_hub_wq hub_event
      Call Trace:
       __dump_stack lib/dump_stack.c:79 [inline]
       dump_stack+0x24c/0x2e0 lib/dump_stack.c:120
       kmsan_report+0xfb/0x1e0 mm/kmsan/kmsan_report.c:118
       __msan_warning+0x5c/0xa0 mm/kmsan/kmsan_instr.c:197
       get_interrupt_interval drivers/net/usb/pegasus.c:746 [inline]
       pegasus_probe+0x10e7/0x4080 drivers/net/usb/pegasus.c:1152
      ....
      
      Local variable ----data.i@pegasus_probe created at:
       get_interrupt_interval drivers/net/usb/pegasus.c:1151 [inline]
       pegasus_probe+0xe57/0x4080 drivers/net/usb/pegasus.c:1152
       get_interrupt_interval drivers/net/usb/pegasus.c:1151 [inline]
       pegasus_probe+0xe57/0x4080 drivers/net/usb/pegasus.c:1152
      
      Reported-and-tested-by: syzbot+02c9f70f3afae308464a@syzkaller.appspotmail.com
      Fixes: 1da177e4 ("Linux-2.6.12-rc2")
      Signed-off-by: NPavel Skripkin <paskripkin@gmail.com>
      Link: https://lore.kernel.org/r/20210804143005.439-1-paskripkin@gmail.comSigned-off-by: NJakub Kicinski <kuba@kernel.org>
      af35fc37
    • G
      net: ethernet: ti: am65-cpsw: fix crash in am65_cpsw_port_offload_fwd_mark_update() · ae03d189
      Grygorii Strashko 提交于
      The am65_cpsw_port_offload_fwd_mark_update() causes NULL exception crash
      when there is at least one disabled port and any other port added to the
      bridge first time.
      
      Unable to handle kernel NULL pointer dereference at virtual address 0000000000000858
      pc : am65_cpsw_port_offload_fwd_mark_update+0x54/0x68
      lr : am65_cpsw_netdevice_event+0x8c/0xf0
      Call trace:
      am65_cpsw_port_offload_fwd_mark_update+0x54/0x68
      notifier_call_chain+0x54/0x98
      raw_notifier_call_chain+0x14/0x20
      call_netdevice_notifiers_info+0x34/0x78
      __netdev_upper_dev_link+0x1c8/0x290
      netdev_master_upper_dev_link+0x1c/0x28
      br_add_if+0x3f0/0x6d0 [bridge]
      
      Fix it by adding proper check for port->ndev != NULL.
      
      Fixes: 2934db9b ("net: ti: am65-cpsw-nuss: Add netdevice notifiers")
      Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ae03d189
    • D
      bnx2x: fix an error code in bnx2x_nic_load() · fb653827
      Dan Carpenter 提交于
      Set the error code if bnx2x_alloc_fw_stats_mem() fails.  The current
      code returns success.
      
      Fixes: ad5afc89 ("bnx2x: Separate VF and PF logic")
      Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fb653827
    • L
      netdevsim: Forbid devlink reload when adding or deleting ports · 23809a72
      Leon Romanovsky 提交于
      In order to remove complexity in devlink core related to
      devlink_reload_enable/disable, let's rewrite new_port/del_port
      logic to rely on internal to netdevsim lcok.
      
      We should protect only reload_down flow because it destroys nsim_dev,
      which is needed for nsim_dev_port_add/nsim_dev_port_del to hold
      port_list_lock.
      Signed-off-by: NLeon Romanovsky <leonro@nvidia.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      23809a72
    • D
      Revert "wwan: mhi: Fix build." · a85b99ab
      David S. Miller 提交于
      This reverts commit ab996c42.
      
      Only aplicable when net is merged into net-next.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a85b99ab
    • D
      wwan: mhi: Fix build. · ab996c42
      David S. Miller 提交于
      Reported-by: NMark Brown <broonie@kernel.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ab996c42
    • M
      net: wwan: iosm: fix recursive lock acquire in unregister · 679505ba
      M Chetan Kumar 提交于
      Calling unregister_netdevice() inside wwan del link is trying to
      acquire the held lock in ndo_stop_cb(). Instead, queue net dev to
      be unregistered later.
      Signed-off-by: NM Chetan Kumar <m.chetan.kumar@linux.intel.com>
      Reviewed-by: NLoic Poulain <loic.poulain@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      679505ba
    • M
      net: wwan: iosm: correct data protocol mask bit · c98f5220
      M Chetan Kumar 提交于
      Correct ul/dl data protocol mask bit to know which protocol capability
      does device implement.
      Signed-off-by: NM Chetan Kumar <m.chetan.kumar@linux.intel.com>
      Reviewed-by: NLoic Poulain <loic.poulain@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c98f5220
    • M
      net: wwan: iosm: endianness type correction · b46c5795
      M Chetan Kumar 提交于
      Endianness type correction for nr_of_bytes. This field is exchanged
      as part of host-device protocol communication.
      Signed-off-by: NM Chetan Kumar <m.chetan.kumar@linux.intel.com>
      Reviewed-by: NLoic Poulain <loic.poulain@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b46c5795
    • M
      net: wwan: iosm: fix lkp buildbot warning · 5a7c1b2a
      M Chetan Kumar 提交于
      Correct td buffer type casting & format specifier to fix lkp buildbot
      warning.
      Reported-by: Nkernel test robot <lkp@intel.com>
      Signed-off-by: NM Chetan Kumar <m.chetan.kumar@linux.intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5a7c1b2a
    • A
      net: ipa: move IPA flags field · afb08b7e
      Alex Elder 提交于
      The ipa->flags field is only ever used in "ipa_clock.c", related to
      suspend/resume activity.
      
      Move the definition of the ipa_flag enumerated type to "ipa_clock.c".
      And move the flags field from the ipa structure and to the ipa_clock
      structure.  Rename the type and its values to include "power" or
      "POWER" in the name.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      afb08b7e
    • A
      net: ipa: move ipa_suspend_handler() · afe1baa8
      Alex Elder 提交于
      Move ipa_suspend_handler() into "ipa_clock.c" from "ipa_main.c", to
      group with the reset of the suspend/resume code.  This IPA interrupt
      is triggered if an IPA RX endpoint is suspended but has a packet to
      be delivered.
      
      Introduce ipa_power_setup() and ipa_power_teardown() to add and
      remove the handler for the IPA SUSPEND interrupt at the same place
      as before, while allowing the handler to remain private.
      
      The "power" naming convention will be adopted elsewhere in this
      file as well (soon).
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      afe1baa8
    • A
      net: ipa: move IPA power operations to ipa_clock.c · 73ff316d
      Alex Elder 提交于
      Move ipa_suspend() and ipa_resume(), as well as the definition of
      the ipa_pm_ops structure into "ipa_clock.c".  Make ipa_pm_ops public
      and declare it as extern in "ipa_clock.h".
      
      This is part of centralizing IPA power management functionality into
      "ipa_clock.c" (the file will eventually get a name change).
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      73ff316d
    • A
      net: ipa: improve IPA clock error messages · 8ee7c40a
      Alex Elder 提交于
      Rearrange messages reported when errors occur in the IPA clock code,
      so that the specific interconnect is identified when an error occurs
      enabling or disabling it, or the core clock is indicated when an
      error occurs enabling it.
      
      Have ipa_interconnect_disable() return zero or the negative error
      value returned by the first interconnect that produced an error
      when disabled.  For now, the callers ignore the returned value.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8ee7c40a
    • A
      net: ipa: reorder netdev pointer assignments · 10cc73c4
      Alex Elder 提交于
      Assign the ipa->modem_netdev and endpoint->netdev pointers *before*
      registering the network device.  As soon as the device is
      registered it can be opened, and by that time we'll want those
      pointers valid.
      
      Similarly, don't make those pointers NULL until *after* the modem
      network device is unregistered in ipa_modem_stop().
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      10cc73c4
    • A
      net: ipa: don't suspend/resume modem if not up · 30c2515b
      Alex Elder 提交于
      The modem network device is set up by ipa_modem_start().  But its
      TX queue is not actually started and endpoints enabled until it is
      opened.
      
      So avoid stopping the modem network device TX queue and disabling
      endpoints on suspend or stop unless the netdev is marked UP.  And
      skip attempting to resume unless it is UP.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      30c2515b
    • V
      net: dsa: sja1105: enable address learning on cascade ports · 81d45898
      Vladimir Oltean 提交于
      Right now, address learning is disabled on DSA ports, which means that a
      packet received over a DSA port from a cross-chip switch will be flooded
      to unrelated ports.
      
      It is desirable to eliminate that, but for that we need a breakdown of
      the possibilities for the sja1105 driver. A DSA port can be:
      
      - a downstream-facing cascade port. This is simple because it will
        always receive packets from a downstream switch, and there should be
        no other route to reach that downstream switch in the first place,
        which means it should be safe to learn that MAC address towards that
        switch.
      
      - an upstream-facing cascade port. This receives packets either:
        * autonomously forwarded by an upstream switch (and therefore these
          packets belong to the data plane of a bridge, so address learning
          should be ok), or
        * injected from the CPU. This deserves further discussion, as normally,
          an upstream-facing cascade port is no different than the CPU port
          itself. But with "H" topologies (a DSA link towards a switch that
          has its own CPU port), these are more "laterally-facing" cascade
          ports than they are "upstream-facing". Here, there is a risk that
          the port might learn the host addresses on the wrong port (on the
          DSA port instead of on its own CPU port), but this is solved by
          DSA's RX filtering infrastructure, which installs the host addresses
          as static FDB entries on the CPU port of all switches in a "H" tree.
          So even if there will be an attempt from the switch to migrate the
          FDB entry from the CPU port to the laterally-facing cascade port, it
          will fail to do that, because the FDB entry that already exists is
          static and cannot migrate. So address learning should be safe for
          this configuration too.
      
      Ok, so what about other MAC addresses coming from the host, not
      necessarily the bridge local FDB entries? What about MAC addresses
      dynamically learned on foreign interfaces, isn't there a risk that
      cascade ports will learn these entries dynamically when they are
      supposed to be delivered towards the CPU port? Well, that is correct,
      and this is why we also need to enable the assisted learning feature, to
      snoop for these addresses and write them to hardware as static FDB
      entries towards the CPU, to make the switch's learning process on the
      cascade ports ineffective for them. With assisted learning enabled, the
      hardware learning on the CPU port must be disabled.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      81d45898
    • V
      net: dsa: sja1105: suppress TX packets from looping back in "H" topologies · 0f9b762c
      Vladimir Oltean 提交于
      H topologies like this one have a problem:
      
               eth0                                                     eth1
                |                                                        |
             CPU port                                                CPU port
                |                        DSA link                        |
       sw0p0  sw0p1  sw0p2  sw0p3  sw0p4 -------- sw1p4  sw1p3  sw1p2  sw1p1  sw1p0
         |             |      |                            |      |             |
       user          user   user                         user   user          user
       port          port   port                         port   port          port
      
      Basically any packet sent by the eth0 DSA master can be flooded on the
      interconnecting DSA link sw0p4 <-> sw1p4 and it will be received by the
      eth1 DSA master too. Basically we are talking to ourselves.
      
      In VLAN-unaware mode, these packets are encoded using a tag_8021q TX
      VLAN, which dsa_8021q_rcv() rightfully cannot decode and complains.
      Whereas in VLAN-aware mode, the packets are encoded with a bridge VLAN
      which _can_ be decoded by the tagger running on eth1, so it will attempt
      to reinject that packet into the network stack (the bridge, if there is
      any port under eth1 that is under a bridge). In the case where the ports
      under eth1 are under the same cross-chip bridge as the ports under eth0,
      the TX packets will even be learned as RX packets. The only thing that
      will prevent loops with the software bridging path, and therefore
      disaster, is that the source port and the destination port are in the
      same hardware domain, and the bridge will receive packets from the
      driver with skb->offload_fwd_mark = true and will not forward between
      the two.
      
      The proper solution to this problem is to detect H topologies and
      enforce that all packets are received through the local switch and we do
      not attempt to receive packets on our CPU port from switches that have
      their own. This is a viable solution which works thanks to the fact that
      MAC addresses which should be filtered towards the host are installed by
      DSA as static MAC addresses towards the CPU port of each switch.
      
      TX from a CPU port towards the DSA port continues to be allowed, this is
      because sja1105 supports bridge TX forwarding offload, and the skb->dev
      used initially for xmit does not have any direct correlation with where
      the station that will respond to that packet is connected. It may very
      well happen that when we send a ping through a br0 interface that spans
      all switch ports, the xmit packet will exit the system through a DSA
      switch interface under eth1 (say sw1p2), but the destination station is
      connected to a switch port under eth0, like sw0p0. So the switch under
      eth1 needs to communicate on TX with the switch under eth0. The
      response, however, will not follow the same path, but instead, this
      patch enforces that the response is sent by the first switch directly to
      its DSA master which is eth0.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0f9b762c
    • V
      net: dsa: sja1105: increase MTU to account for VLAN header on DSA ports · 777e55e3
      Vladimir Oltean 提交于
      Since all packets are transmitted as VLAN-tagged over a DSA link (this
      VLAN tag represents the tag_8021q header), we need to increase the MTU
      of these interfaces to account for the possibility that we are already
      transporting a user-visible VLAN header.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      777e55e3
    • V
      net: dsa: sja1105: manage VLANs on cascade ports · c5130029
      Vladimir Oltean 提交于
      Since commit ed040abc ("net: dsa: sja1105: use 4095 as the private
      VLAN for untagged traffic"), this driver uses a reserved value as pvid
      for the host port (DSA CPU port). Control packets which are sent as
      untagged get classified to this VLAN, and all ports are members of it
      (this is to be expected for control packets).
      
      Manage all cascade ports in the same way and allow control packets to
      egress everywhere.
      
      Also, all VLANs need to be sent as egress-tagged on all cascade ports.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c5130029
    • V
      net: dsa: sja1105: manage the forwarding domain towards DSA ports · 3fa21270
      Vladimir Oltean 提交于
      Manage DSA links towards other switches, be they host ports or cascade
      ports, the same as the CPU port, i.e. allow forwarding and flooding
      unconditionally from all user ports.
      
      We send packets as always VLAN-tagged on a DSA port, and we rely on the
      cross-chip notifiers from tag_8021q to install the RX VLAN of a switch
      port only on the proper remote ports of another switch (the ports that
      are in the same bridging domain). So if there is no cross-chip bridging
      in the system, the flooded packets will be sent on the DSA ports too,
      but they will be dropped by the remote switches due to either
      (a) a lack of the RX VLAN in the VLAN table of the ingress DSA port, or
      (b) a lack of valid destinations for those packets, due to a lack of the
          RX VLAN on the user ports of the switch
      
      Note that switches which only transport packets in a cross-chip bridge,
      but have no user ports of their own as part of that bridge, such as
      switch 1 in this case:
      
                          DSA link                   DSA link
        sw0p0 sw0p1 sw0p2 -------- sw1p0 sw1p2 sw1p3 -------- sw2p0 sw2p2 sw2p3
      
      ip link set sw0p0 master br0
      ip link set sw2p3 master br0
      
      will still work, because the tag_8021q cross-chip notifiers keep the RX
      VLANs installed on all DSA ports.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3fa21270
    • V
      net: dsa: sja1105: configure the cascade ports based on topology · 30a100e6
      Vladimir Oltean 提交于
      The sja1105 switch family has a feature called "cascade ports" which can
      be used in topologies where multiple SJA1105/SJA1110 switches are daisy
      chained. Upstream switches set this bit for the DSA link towards the
      downstream switches. This is used when the upstream switch receives a
      control packet (PTP, STP) from a downstream switch, because if the
      source port for a control packet is marked as a cascade port, then the
      source port, switch ID and RX timestamp will not be taken again on the
      upstream switch, it is assumed that this has already been done by the
      downstream switch (the leaf port in the tree) and that the CPU has
      everything it needs to decode the information from this packet.
      
      We need to distinguish between an upstream-facing DSA link and a
      downstream-facing DSA link, because the upstream-facing DSA links are
      "host ports" for the SJA1105/SJA1110 switches, and the downstream-facing
      DSA links are "cascade ports".
      
      Note that SJA1105 supports a single cascade port, so only daisy chain
      topologies work. With SJA1110, there can be more complex topologies such
      as:
      
                          eth0
                           |
                       host port
                           |
       sw0p0    sw0p1    sw0p2    sw0p3    sw0p4
         |        |                 |        |
       cascade  cascade            user     user
        port     port              port     port
         |        |
         |        |
         |        |
         |       host
         |       port
         |        |
         |      sw1p0    sw1p1    sw1p2    sw1p3    sw1p4
         |                 |        |        |        |
         |                user     user     user     user
        host              port     port     port     port
        port
         |
       sw2p0    sw2p1    sw2p2    sw2p3    sw2p4
                  |        |        |        |
                 user     user     user     user
                 port     port     port     port
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      30a100e6