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  1. 19 6月, 2015 3 次提交
  3. 12 6月, 2015 1 次提交
  5. 03 6月, 2015 10 次提交
  7. 13 5月, 2015 2 次提交
  9. 09 5月, 2015 1 次提交
  11. 07 5月, 2015 1 次提交
  13. 05 5月, 2015 1 次提交
  15. 01 5月, 2015 2 次提交
  17. 29 4月, 2015 5 次提交
  19. 17 4月, 2015 1 次提交
  21. 13 4月, 2015 4 次提交
  23. 11 4月, 2015 4 次提交
  25. 10 4月, 2015 5 次提交
    • T
      clk: tegra: Use the proper parent for plld_dsi · c1d676ce
      由 Thierry Reding 提交于 
      The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.

Fixes: b270491e ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: NThierry Reding <treding@nvidia.com>
      c1d676ce
    • T
      clk: tegra: Use generic tegra_osc_clk_init() on Tegra114 · a84724a1
      由 Thierry Reding 提交于 
      There is no reason why Tegra114 cannot use the same generic code to set
up the oscillator, clk_m and pll_ref clocks. The only effective change
that this causes is that the CLK_SET_PARENT_RATE flag is dropped, but
since these clocks are all fixed it is not needed anyway.
Signed-off-by: NThierry Reding <treding@nvidia.com>
      a84724a1
    • T
      clk: tegra: Model oscillator as clock · 63cc5a4d
      由 Thierry Reding 提交于 
      Currently the Tegra clock driver simplifies the clock tree somewhat by
taking advantage of the fact that clk_m runs at the same frequency as
the oscillator. While that's true on all currently supported SoCs, it
does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
divided down from the oscillator frequency. To support that setup, add
a separate clock for the oscillator that both clk_m and pll_ref derive
from.

Modify the tegra_osc_clk_init() function to take an additional divider
parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
will read the divider from a register in the clock & reset controller.
Signed-off-by: NThierry Reding <treding@nvidia.com>
      63cc5a4d
    • T
      clk: tegra: Add peripheral registers for bank Y · 699b477a
      由 Thierry Reding 提交于 
      Tegra210 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
      699b477a
    • T
      clk: tegra: Register the proper number of resets · 5e43e259
      由 Thierry Reding 提交于 
      The number of resets controls is 32 times the number of peripheral
register banks rather than 32 times the number of clocks. This reduces
(drastically) the number of reset controls registered from 10080 (315
clocks * 32) to 224 (6 peripheral register banks * 32).

This also fixes a potential crash because trying to use any of the
excess reset controls (224-10079) would have caused accesses beyond
the array bounds of the peripheral register banks definition array.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Fixes: 6d5b988e ("clk: tegra: implement a reset driver")
Cc: stable@vger.kernel.org # 3.14+
Signed-off-by: NThierry Reding <treding@nvidia.com>
      5e43e259