The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.

Assume that the second controller has the same fault, but that is
untested.
Signed-off-by: NPeter Rosin <peda@axentia.se>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if
something went wrong instead of continuing in unknown condition. There
is not much we can do if a PLL lock never ends, we are running in SRAM
and we will not be able to connect back the sdram or ddram in order to
be able to fire up a message or just panic.

As a bonus, not decounting the timeout register in slow clock mode
reduce cumulated suspend time and resume time from ~17ms to ~15ms.
Signed-off-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: NWenyou.Yang <wenyou.yang@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The SOC_AT91SAM9263 is being removed, stop using it.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91_pmc.h).
We need this to avoid reference to machine specific headers in clk
drivers.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NFelipe Balbi <balbi@ti.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

We can now compile all SoC core support together and DT boards.
We still can not compile together the non DT board.
So We keep the ARCH_AT91xxx for the non DT board and for backward defconfig
compatibility. This will enable the plaform_device ressources.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: NRyan Mallon <rmallon@gmail.com>

This will allow to have all SoC in one kernel image.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This cleanup is done to allow to have multiple SoC in the same image.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Change slow_clock()/at91_slow_clock() prototype to accept the PMC
base address and one or two RAM controller addresses by parameters.
The r0, r1 and r2 registers are used differently and preserved during
function call.
Those values are defined in pm.c and slow_clock() function is called
from there with its new parameters.

This will allow to have a soc independent pm_slowclock.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Ached-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This patch will give a name to ARM registers in the assembly
source code. It is done to simplify the code reading and
the passing of parameters to functions.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Following removal announce and addition to feature-removal-schedule.txt,
here is the actual source code deletion for Atmel CAP9 family.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

When using CP15 cache operations (c7), we make sure that Rd (r0)
is actually 0 as ARM 926 TRM is saying.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This rework allows to address tow memory controllers. AT91SAM9263 and
AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management
should take care of this.
This patch modify the way RAM IP header files are implemented to allow
access to registers of both controllers ; it also adds some macros.

We also modify the power management files to use those modified header files.
Slow clock (assembly) and regular power management functions are synchronized
for setting of RAM self-refresh procedure:
(lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESH

Note that AT91RM9200 is not impacted by this modification.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

From: Julien Langer <julien.langer@gmail.com>

AT91: when turning off the PLLs during suspend, don't wait for the lock
flag to be set. Previously the code would always run into the loop
limitation of 1000 iterations because the flag is never set when turning
the PLLs off.

Comments from Anders Larsen:

 (in http://marc.info/?l=linux-kernel&m=127058929724193&w=2)
Signed-off-by: NJulien Langer <julien.langer@gmail.com>
Signed-off-by: NAnders Larsen <al@alarsen.net>
Acked-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

at91 slow-clock resume: Don't wait for a disabled PLL to lock.

We run into this problem with the PLLB on the at91: ohci-at91 disables
the PLLB when going to suspend. The slowclock code however tries to do
the same: It saves the PLLB register value and when restoring the value
during resume, it waits for the PLLB to lock again. However the PLL will
never lock and the loop would run into its timeout because the slowclock
code just stored and restored an empty register.
This fixes the problem by only restoring PLLA/PLLB when they were enabled
at suspend time.

Cc: Andrew Victor <avictor.za@gmail.com>
Signed-off-by: NAnders Larsen <al@alarsen.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds support for a low(er)-power suspend-to-RAM.
In addition to the SDRAM being put into self-refresh mode, the Master
Clock is set to the Slow-clock rate (32Khz) and PLLA & PLLB are
disabled.
Certain peripherals are therefore also disabled, and thus cannot be
used as wakeup sources.

This patch has been included in the AT91 patches in various forms
since 2.6.19 and a number of people have worked or commented on it,
most notably:
 Savin Zlobec (for the original AT91RM9200 support)
 Anti Sullin (for the SAM9260 version)
 David Brownell, etc.
Signed-off-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>