- 03 11月, 2014 2 次提交
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由 Sebastian Hesselbarth 提交于
Armada XP pinctrl node gained an alias, make use of it. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-By: NBenoit Masson <yahoo@perenite.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
In other MVEBU SoCs, the pin controller node is called pin-ctrl with its base address added. Also, we have a node alias to access the pinctrl node easily. Fix this for Armada XP pinctrl nodes to be consistent with other SoCs. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-By: NBenoit Masson <yahoo@perenite.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 17 6月, 2014 1 次提交
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由 Jason Cooper 提交于
The OpenBlocks AX3-4 has a non-DT bootloader. It also comes with 1GB of soldered on RAM, and a DIMM slot for expansion. Unfortunately, atags_to_fdt() doesn't work in big-endian mode, so we see the following failure when attempting to boot a big-endian kernel: 686 slab pages 17 pages shared 0 pages swap cached [ pid ] uid tgid total_vm rss nr_ptes swapents oom_score_adj name Kernel panic - not syncing: Out of memory and no killable processes... CPU: 1 PID: 351 Comm: kworker/u4:0 Not tainted 3.15.0-rc8-next-20140603 #1 [<c0215a54>] (unwind_backtrace) from [<c021160c>] (show_stack+0x10/0x14) [<c021160c>] (show_stack) from [<c0802500>] (dump_stack+0x78/0x94) [<c0802500>] (dump_stack) from [<c0800068>] (panic+0x90/0x21c) [<c0800068>] (panic) from [<c02b5704>] (out_of_memory+0x320/0x340) [<c02b5704>] (out_of_memory) from [<c02b93a0>] (__alloc_pages_nodemask+0x874/0x930) [<c02b93a0>] (__alloc_pages_nodemask) from [<c02d446c>] (handle_mm_fault+0x744/0x96c) [<c02d446c>] (handle_mm_fault) from [<c02cf250>] (__get_user_pages+0xd0/0x4c0) [<c02cf250>] (__get_user_pages) from [<c02f3598>] (get_arg_page+0x54/0xbc) [<c02f3598>] (get_arg_page) from [<c02f3878>] (copy_strings+0x278/0x29c) [<c02f3878>] (copy_strings) from [<c02f38bc>] (copy_strings_kernel+0x20/0x28) [<c02f38bc>] (copy_strings_kernel) from [<c02f4f1c>] (do_execve+0x3a8/0x4c8) [<c02f4f1c>] (do_execve) from [<c025ac10>] (____call_usermodehelper+0x15c/0x194) [<c025ac10>] (____call_usermodehelper) from [<c020e9b8>] (ret_from_fork+0x14/0x3c) CPU0: stopping CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.15.0-rc8-next-20140603 #1 [<c0215a54>] (unwind_backtrace) from [<c021160c>] (show_stack+0x10/0x14) [<c021160c>] (show_stack) from [<c0802500>] (dump_stack+0x78/0x94) [<c0802500>] (dump_stack) from [<c021429c>] (handle_IPI+0x138/0x174) [<c021429c>] (handle_IPI) from [<c02087f0>] (armada_370_xp_handle_irq+0xb0/0xcc) [<c02087f0>] (armada_370_xp_handle_irq) from [<c0212100>] (__irq_svc+0x40/0x50) Exception stack(0xc0b6bf68 to 0xc0b6bfb0) bf60: e9fad598 00000000 00f509a3 00000000 c0b6a000 c0b724c4 bf80: c0b72458 c0b6a000 00000000 00000000 c0b66da0 c0b6a000 00000000 c0b6bfb0 bfa0: c027bb94 c027bb24 60000313 ffffffff [<c0212100>] (__irq_svc) from [<c027bb24>] (cpu_startup_entry+0x54/0x214) [<c027bb24>] (cpu_startup_entry) from [<c0ac5b30>] (start_kernel+0x318/0x37c) [<c0ac5b30>] (start_kernel) from [<00208078>] (0x208078) ---[ end Kernel panic - not syncing: Out of memory and no killable processes... A similar failure will also occur if ARM_ATAG_DTB_COMPAT isn't selected. Fix this by setting a sane default (1 GB) in the dts file. Signed-off-by: NJason Cooper <jason@lakedaemon.net> Tested-by: NKevin Hilman <khilman@linaro.org> Cc: <stable@vger.kernel.org> #v3.13+ Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 26 4月, 2014 2 次提交
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由 Thomas Petazzoni 提交于
Now that the Armada 370/375/38x/XP SoC-level Device Tree files have the proper "clocks" property in their UART controllers node, it is no longer useful to have the clock-frequency property defined in the board-level Device Tree files. Therefore, this commit gets rid of all the useless 'clock-frequency' properties. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397806908-7550-5-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
The mvebu-devbus driver had a serious bug, which lead to a 8 bits bus width declared in the Device Tree being considered as a 16 bits bus width when configuring the hardware. This bug in mvebu-devbus driver was compensated by a symetric mistake in the Armada XP OpenBlocks AX3 Device Tree: a 8 bits bus width was declared, even though the hardware actually has a 16 bits bus width connection with the NOR flash. Now that we have fixed the mvebu-devbus driver to behave according to its Device Tree binding, this commit fixes the problematic Device Tree files as well. This bug was introduced in commit a7d4f818 ('ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board') which was merged in v3.10. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397489361-5833-5-git-send-email-thomas.petazzoni@free-electrons.com Fixes: a7d4f818 ('ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board') Cc: stable@vger.kernel.org # v3.10+ Acked-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 12 2月, 2014 2 次提交
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由 Thomas Petazzoni 提交于
Instead of harcoding keycodes specifications in the Armada 370/XP boards, use the <dt-bindings/input/input.h> header file and its keycode definitions. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
Instead of harcoding 0 and 1 for the gpio specifications in the Armada 370/XP boards, use the <dt-bindings/gpio/gpio.h> header file and its GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW definitions. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 24 11月, 2013 1 次提交
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由 Jason Cooper 提交于
Generally, power LEDs should indicate when power is applied, and go out once power is removed. _Not_ annoy the developer with migraine-inducing blinking reminicent of some badly animated television series designed to sell sugar to children. On a more serious note, most of these OS-specific properties aren't necessary and should be removed. I left two that are legitimately tying disk LEDs to disk activity. Other than that, we keep the state the bootloader left them in until userspace changes the state via sysfs. Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 06 8月, 2013 5 次提交
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由 Ezequiel Garcia 提交于
Now that mbus has been added to the device tree, it's possible to move the PCIe nodes out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Moving the PCIe nodes, we now need to introduce an extra cell to encode the window target ID and attribute. Since this depends on the PCIe port, we split the ranges translation entries, to correspond to each MBus window. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
Now that mbus has been added to the device tree, it's possible to move the DeviceBus out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
In order to access the SoC BootROM, we need to declare a mapping (through a ranges property). The mbus driver will use this property to allocate a suitable address decoding window. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
The Armada 370/XP SoC family has a completely configurable address space handled by the MBus controller. This patch introduces the device tree layout of MBus, making the 'soc' node as mbus-compatible. Since every peripheral/controller is a child of this 'soc' node, this makes all of them sit behind the mbus, thus describing the hardware accurately. A translation entry has been added for the internal-regs mapping. This can't be done in the common armada-370-xp.dtsi because A370 and AXP have different addressing width. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 07 6月, 2013 1 次提交
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由 Thomas Petazzoni 提交于
The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 21 5月, 2013 1 次提交
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由 Thomas Petazzoni 提交于
Besides the two "classic" USB interfaces with normal USB ports on the front side, the PlatHome OpenBlocks AX3 uses the third USB interface of the Marvell SoC in the mini-PCIe connector. This allows certain mini-PCIe cards to expose parts of their functionality as a USB peripheral. This commit enables this third USB interface in the OpenBlocks AX3 Device Tree, and also adds comments on top of the two other USB interfaces so that the Device Tree makes it clear which USB interface at the SoC level matches which USB interface visible on the board. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NAtsushi Yamagata <yamagata@plathome.co.jp> Tested-by: NWilly Tarreau <w@1wt.eu> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 14 5月, 2013 1 次提交
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由 Ezequiel Garcia 提交于
With the latest device tree reorganization which introduced the 'internal-reg' node, now the only region translated is the internal register's. This makes the description of the hardware incomplete, for it lacks the Device Bus childs address space. In order to fix this, it's required to add a 'ranges' entry with a suitable address space to map Device Bus childs, on a per-board basis. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 15 4月, 2013 4 次提交
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由 Gregory CLEMENT 提交于
In order to be able to use more than 4GB of RAM when the LPAE is activated, the dts must be converted in 64 bits. Only Armada XP is LPAE capable, but as it shares a common dtsi file with Armada 370, then the common file include the skeleton64. Thanks to the use of the overload capability of the device tree format, armada-370 include the 32 bit skeleton and all the armada 370 based dts can remain the same. This was heavily based on the work of Lior Amsalem. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
Introduce a 'internal-regs' subnode, under which all devices are moved. This is not really needed for now, but will be for the mvebu-mbus driver. This generates a lot of code movement since it's indenting by one more tab all the devices. So it was a good opportunity to fix all the bad indentation. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
This conversion will allow to keep 32 bits addresses for the internal registers whereas the memory of the system will be 64 bits. Later it will also ease the move of the mvebu-mbus driver to the device tree support. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can be used to plug mini-PCIe devices. We therefore enable the PCIe interface that corresponds to this slot. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 12 4月, 2013 1 次提交
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由 Ezequiel Garcia 提交于
The Plat'home Openblocks AX3 has a 128 MiB NOR flash device connected to the Device Bus. This commit adds the device tree node to support this device. The SoC supports a flexible and dynamic decoding window allocation scheme; but since this feature is still not implemented we need to specify the window base address in the device tree node itself. This base address has been selected in a completely arbitrary fashion. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 01 3月, 2013 2 次提交
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由 Ezequiel Garcia 提交于
This patch activates every USB port provided by each SoC. Except for Armada XP Openblocks AX3-4 board, where we enable only the first two USB ports until we have more information on the third one usage. Cc: Lior Amsalem <alior@marvell.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> Tested-by: NFlorian Fainelli <florian@openwrt.org> Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
The OpenBlocks AX3-4 board has one software-controlled button on the front side, labeled "INIT", so we add minimal support for this button in the kernel. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 22 11月, 2012 3 次提交
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由 Thomas Petazzoni 提交于
This patch enables SATA support on the OpenBlocks AX3-4. It has one internal SATA port, and an external eSATA port. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
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由 Nobuhiro Iwamatsu 提交于
The OpenBlocks AX3-4 has a Seiko Instruments S-35390A as the RTC controller. This patch enables this RTC device in the OpenBlocks AX3-4 Device Tree. [Thomas Petazzoni: updated with other OpenBlocks changes, rephrased commit log.] Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
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由 Nobuhiro Iwamatsu 提交于
The OpenBlocks AX3-4 board, based on the Armada XP SoC, has an I2C bus. This patch enables this bus and sets the clock frequency of the bus. [Thomas Petazzoni: updated with other changes on OpenBlocks, rephrased commit log.] Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
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- 21 11月, 2012 1 次提交
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由 Thomas Petazzoni 提交于
The mvneta driver for the Marvell Armada 370/XP Ethernet devices has gained proper clock framework integration, and the corresponding Device Tree nodes now have a correct 'clocks' pointer. The 'clock-frequency' properties in the various .dts files for Armada 370/XP boards have therefore become useless. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
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- 16 11月, 2012 1 次提交
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由 Thomas Petazzoni 提交于
The PlatHome OpenBlocks AX3-4 platform has 4 Ethernet ports, connected to a single quad-port PHY through SGMII. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
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- 14 11月, 2012 1 次提交
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由 Thomas Petazzoni 提交于
This platform, available in Japan from PlatHome, has a dual-core Armada XP, the MV78260. For now, only the two serial ports and the three front LEDs are supported. Support for SMP, network, SATA, USB and other peripherals will be added as drivers for them become available for Armada XP in mainline. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com> --- This is 3.8 material. Changes since v2: * Renamed the .dts file to armada-xp-openblocks-ax3-4.dts * Removed the compatible string from armada-370-xp.c (which now only lists the common SoC compatible string) Changes since v1: * Renamed the board to OpenBlocks AX3-4, since there is a variant called AX3-2 which has less RAM, and no mini PCIe port. Requested by Andrew Lunn. * Fix the amount of memory to 3 GB. In fact, the board has 1 GB soldered, and 2 GB in a SODIMM slot (which is therefore removable). But as the board is delivered as is, we'll assume it has 3 GB of memory by default.
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