- 27 5月, 2022 2 次提交
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由 Michael Walle 提交于
The Kontron KSwitch D10 is based on a Microchip LAN9668 SoC. It is a managed ethernet network switch with either 8 copper ports or 6 copper ports and 2 SFP cages. Enable all required kconfig symbols, either as module where possible or compiled-in where it is not possible. Signed-off-by: NMichael Walle <michael@walle.cc> Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220518141542.531148-1-michael@walle.cc' Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Genjian Zhang 提交于
Avoid return freed memory addresses,Modified to the actual error return value of clk_register(). Fixes: 9645ccc7 ("ep93xx: clock: convert in-place to COMMON_CLK") Signed-off-by: NGenjian Zhang <zhanggenjian@kylinos.cn> Acked-by: NAlexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 25 5月, 2022 1 次提交
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由 Linus Walleij 提交于
The IXP4xx Kconfig we ended up with for mach-ixp4xx creates as kismet warning: WARNING: unmet direct dependencies detected for GPIO_IXP4XX Depends on [n]: GPIOLIB [=y] && HAS_IOMEM [=y] && ARCH_IXP4XX [=y] && OF [=n] Selected by [y]: - ARCH_IXP4XX [=y] && <choice> This is because it is possible to select ARCH_IXP4XX witout OF while that selects the GPIO driver that now depends on OF. Fix this by creating a single ARCH_IXP4XX kconfig that selects USE_OF. Reported-by: Nkernel test robot <lkp@intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Krzysztof Halasa <khalasa@piap.pl> Link: https://lore.kernel.org/r/20220522072356.34062-1-linus.walleij@linaro.org' Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 20 5月, 2022 8 次提交
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由 Chen Zhongjin 提交于
For EABI stack unwinding, when loading .ko module the EXIDX sections will be added to a unwind_table list. However not all EXIDX sections are added because EXIDX sections are searched by hardcoded section names. For functions in other sections such as .ref.text or .kprobes.text, gcc generates seprated EXIDX sections (such as .ARM.exidx.ref.text or .ARM.exidx.kprobes.text). These extra EXIDX sections are not loaded, so when unwinding functions in these sections, we will failed with: unwind: Index not found xxx To fix that, I refactor the code for searching and adding EXIDX sections: - Check section type to search EXIDX tables (0x70000001) instead of strcmp() the hardcoded names. Then find the corresponding text sections by their section names. - Add a unwind_table list in module->arch to save their own unwind_table instead of the fixed-lenth array. - Save .ARM.exidx.init.text section ptr, because it should be cleaned after module init. Now all EXIDX sections of .ko can be added correctly. Signed-off-by: NChen Zhongjin <chenzhongjin@huawei.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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由 Nick Hawkins 提交于
Enable the workaround for the 764319 Cortex A-9 erratum. CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an unexpected Undefined Instruction exception when the DBGSWENABLE external pin is set to 0, even when the CP14 accesses are performed from a privileged mode. The work around catches the exception in a way the kernel does not stop execution with the use of undef_hook. This has been found to effect the HPE GXP SoC. Signed-off-by: NNick Hawkins <nick.hawkins@hpe.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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由 Ard Biesheuvel 提交于
The assembler does not permit 'LDR PC, <sym>' when the symbol lives in a different section, which is why we have been relying on rather fragile open-coded arithmetic to load the address of the vector_swi routine into the program counter using a single LDR instruction in the SWI slot in the vector table. The literal was moved to a different section to in commit 19accfd3 ("ARM: move vector stubs") to ensure that the vector stubs page does not need to be mapped readable for user space, which is the case for the vector page itself, as it carries the kuser helpers as well. So the cross-section literal load is open-coded, and this relies on the address of vector_swi to be at the very start of the vector stubs page, and we won't notice if we got it wrong until booting the kernel and see it break. Fortunately, it was guaranteed to break, so this was fragile but not problematic. Now that we have added two other variants of the vector table, we have 3 occurrences of the same trick, and so the size of our ISA/compiler/CPU validation space has tripled, in a way that may cause regressions to only be observed once booting the image in question on a CPU that exercises a particular vector table. So let's switch to true cross section references, and let the linker fix them up like it fixes up all the other cross section references in the vector page. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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由 Ard Biesheuvel 提交于
In order to minimize potential confusion regarding numbered labels appearing in a different order in the assembler output due to the use of subsections, use a named local label to jump back into the vector handler code from the associated loop8 mitigation sequence. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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由 Ard Biesheuvel 提交于
The loop8 mitigation for Spectre-BHB only requires a CPU local DSB rather than a systemwide one, which is much more costly. And by the same reasoning as why it is justified to omit the ISB after BPIALL, we can also elide the ISB and rely on the exception return for the context synchronization. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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由 Ard Biesheuvel 提交于
The BPIALL mitigation for Spectre-BHB adds a single instruction to the handler sequence that doesn't clobber any registers. Given that these sequences are 10 instructions long, they don't fit neatly into a cacheline anyway, so we can simply move that single instruction to the start of the unmitigated one, and rearrange the symbol names accordingly. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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由 Ard Biesheuvel 提交于
ARMv7 has MOVW/MOVT instruction pairs to load symbol addresses into registers without having to rely on literal loads that go via the D-cache. For older cores, we now support a similar arrangement, based on PC-relative group relocations. This means we can elide most literal loads entirely from the entry path, by switching to the ldr_va macro to emit the appropriate sequence depending on the target architecture revision. While at it, switch to the bl_r macro for invoking the right PABT/DABT helpers instead of setting the LR register explicitly, which does not play well with cores that speculate across function returns. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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由 Ard Biesheuvel 提交于
When CONFIG_SMP is not defined, the CPU offset is always zero, and so we can simplify the sequence to load a per-CPU variable. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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- 19 5月, 2022 1 次提交
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由 Josua Mayer 提交于
Since SoM revision 1.9 the PHY has been replaced with an ADIN1300, add an entry for it next to the original. As Russell King pointed out, additional phy nodes cause warnings like: mdio_bus 2188000.ethernet-1: MDIO device at address 1 is missing To avoid this the new node has its status set to disabled. U-Boot will be modified to enable the appropriate phy node after probing. The existing ar8035 nodes have to stay enabled by default to avoid breaking existing systems when they update Linux only. Co-developed-by: NAlvaro Karsz <alvaro.karsz@solid-run.com> Signed-off-by: NAlvaro Karsz <alvaro.karsz@solid-run.com> Signed-off-by: NJosua Mayer <josua@solid-run.com> Signed-off-by: NJakub Kicinski <kuba@kernel.org>
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- 18 5月, 2022 5 次提交
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由 Nick Hawkins 提交于
The HPE SoC is new to linux. A basic device tree layout with minimum required for linux to boot including a timer and watchdog support has been created. The dts file is empty at this point but will be updated in subsequent updates as board specific features are enabled. Signed-off-by: NNick Hawkins <nick.hawkins@hpe.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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由 Nick Hawkins 提交于
Enable HPE GXP Architecture and its watchdog for base support for HPE GXP SoCs. Signed-off-by: NNick Hawkins <nick.hawkins@hpe.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Nick Hawkins 提交于
The GXP is the HPE BMC SoC that is used in the majority of current generation HPE servers. Traditionally the asic will last multiple generations of server before being replaced. Info about SoC: HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC features at HPE. It supports ARMv7 architecture based on the Cortex A9 core. It is capable of using an AXI bus to whicha memory controller is attached. It has multiple SPI interfaces to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple i2c engines to drive connectivity with a host infrastructure. There currently are no public specifications but this process is being worked. Previously there was a requirement to reset the EHCI controller for the asic to boot. This functionality has been moved to the u-boot bootloader. Signed-off-by: NNick Hawkins <nick.hawkins@hpe.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Ard Biesheuvel 提交于
In Thumb2, 'b . + 4' produces a branch instruction that uses a narrow encoding, and so it does not jump to the following instruction as expected. So use W(b) instead. Fixes: 6c7cb60b ("ARM: fix Thumb2 regression with Spectre BHB") Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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由 Ard Biesheuvel 提交于
The Spectre-BHB mitigations were inadvertently left disabled for Cortex-A15, due to the fact that cpu_v7_bugs_init() is not called in that case. So fix that. Fixes: b9baf5c8 ("ARM: Spectre-BHB workaround") Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
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- 17 5月, 2022 6 次提交
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由 Codrin Ciubotariu 提交于
SAMA7G5-EK has 4 PDM microphones connected to PDMC0. PDMC0 pinmux is in conflict with gmac1, gmac1 being enabled by default. Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/all/20220307122202.2251639-6-codrin.ciubotariu@microchip.comSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Codrin Ciubotariu 提交于
Microchip's SAMA7G5 embeds two PDMCs. The PDMCs can be used to connect 2x4 PDM microphones. Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/all/20220307122202.2251639-5-codrin.ciubotariu@microchip.comSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Sergiu Moga 提交于
As the DT specification recommends, the node names should be of a generic nature. Thus, the most appropriate generic node name for the at91 rtt IPs is the "rtc" node name. Signed-off-by: NSergiu Moga <sergiu.moga@microchip.com> Reviewed-by: NKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/all/20220304161159.147784-3-sergiu.moga@microchip.comSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Sergiu Moga 提交于
Add the required 'atmel,rtt-rtc-time-reg' property to the "rtt" nodes of the board files that were missing it. Signed-off-by: NSergiu Moga <sergiu.moga@microchip.com> Reviewed-by: NTudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/all/20220304161159.147784-2-sergiu.moga@microchip.comSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 YueHaibing 提交于
If ATMEL_PM is y but PM is n, build fails: arch/arm/mach-at91/pm.c:1435:13: error: redefinition of 'at91rm9200_pm_init' void __init at91rm9200_pm_init(void) ^~~~~~~~~~~~~~~~~~ In file included from arch/arm/mach-at91/pm.c:29:0: arch/arm/mach-at91/generic.h:19:27: note: previous definition of 'at91rm9200_pm_init' was here static inline void __init at91rm9200_pm_init(void) { } ^~~~~~~~~~~~~~~~~~ ATMEL_PM should not be enabled independently, it is only selected by Soc. Fixes: f2f5cf78 ("ARM: at91: pm: add support for sama5d2 secure suspend") Signed-off-by: NYueHaibing <yuehaibing@huawei.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220517031606.11628-1-yuehaibing@huawei.comSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Samuel Holland 提交于
Not all of these drivers are needed on every ARCH_SUNXI platform. In particular, the ARCH_SUNXI symbol will be reused for the Allwinner D1, a RISC-V SoC which contains none of these irqchips. Introduce Kconfig symbols so we can select only the drivers actually used by a particular set of platforms. This also lets us move the irqchip driver dependencies to a more appropriate location. Signed-off-by: NSamuel Holland <samuel@sholland.org> Signed-off-by: NMarc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220509034941.30704-1-samuel@sholland.org
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- 15 5月, 2022 1 次提交
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由 Mark Rutland 提交于
There are cases where a context synchronization event is necessary between an IRQ being raised and being handled, and there are races such that we cannot rely upon the exception entry being subsequent to the interrupt being raised. To fix this, we place an ISB between a read of IAR and the subsequent invocation of an IRQ handler. When EOI mode 1 is in use, we need to EOI an interrupt prior to invoking its handler, and we have a write to EOIR for this. As this write to EOIR requires an ISB, and this is provided by the gic_write_eoir() helper, we omit the usual ISB in this case, with the logic being: | if (static_branch_likely(&supports_deactivate_key)) | gic_write_eoir(irqnr); | else | isb(); This is somewhat opaque, and it would be a little clearer if there were an unconditional ISB, with only the write to EOIR being conditional, e.g. | if (static_branch_likely(&supports_deactivate_key)) | write_gicreg(irqnr, ICC_EOIR1_EL1); | | isb(); This patch rewrites the code that way, with this logic factored into a new helper function with comments explaining what the ISB is for, as were originally laid out in commit: 39a06b67 ("irqchip/gic: Ensure we have an ISB between ack and ->handle_irq") Note that since then, we removed the IAR polling in commit: 342677d7 ("irqchip/gic-v3: Remove acknowledge loop") ... which removed one of the two race conditions. For consistency, other portions of the driver are made to manipulate EOIR using write_gicreg() and explcit ISBs, and the gic_write_eoir() helper function is removed. There should be no functional change as a result of this patch. Signed-off-by: NMark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: NMarc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220513133038.226182-3-mark.rutland@arm.com
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- 14 5月, 2022 1 次提交
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由 Jason A. Donenfeld 提交于
In the event that random_get_entropy() can't access a cycle counter or similar, falling back to returning 0 is really not the best we can do. Instead, at least calling random_get_entropy_fallback() would be preferable, because that always needs to return _something_, even falling back to jiffies eventually. It's not as though random_get_entropy_fallback() is super high precision or guaranteed to be entropic, but basically anything that's not zero all the time is better than returning zero all the time. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Arnd Bergmann <arnd@arndb.de> Reviewed-by: NRussell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: NJason A. Donenfeld <Jason@zx2c4.com>
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- 13 5月, 2022 15 次提交
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由 Michael Walle 提交于
Enable all the necessary network related nodes, wire the pinctrl configurations, add the PHYs and connect them to the corresponding network ports. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-14-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add the switch node and its 8 children ports. All are disabled by default. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-13-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add the SerDes node. On the LAN966x SoC these SerDes are used to connect network PHYs. By default, that node is disabled. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-12-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add the switch reset node which will later be used by the switch driver. The switch reset also resets the GPIO controller and the SGPIO controller, thus it also has to be connectected to these nodes. This way the reset will only issued once for the first device requesting the reset. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-11-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add the MDIO controller nodes. The integrated PHYs are connected to the second controller. This controller also takes care of the resets of the integrated PHYs, thus it has two memory regions. The first controller is routed to the external MDIO/MDC pins. By default, they are disabled. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-10-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add the monitoring node which covers the temperature sensor as well as the PWM controller and the FAN tacho input. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-9-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add basic support for the Kontron KSwitch D10 MMT. It comes in two variants: "6G-2GS" which features 6 Gigabit copper ports and two SFP cages and "8G" which features 6 Gigbabit copper ports (where two are 2.5G capable). For now the following is supported and working: - Kernel console - SFP cages - SPI - SGPIO - Watchdog Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> [claudiu.beznea: fixed conflict on Makefile] Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-8-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add all I2C nodes of the flexcom IP blocks. The driver supports FIFO, DMA or both combined. But the latter isn't working correctly. Thus, skip the fifo-size property for now. DMA is doing single byte reads in this case. Keep the nodes disabled by default. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-7-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add all the SPI nodes for the flexcom IP block. Keep them disabled by default. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-6-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add all the remaining usart nodes for the flexcom block. Although the DMA channels are specified, DMA is not enabled by default because break detection doesn't work with DMA. Keep the nodes disabled by default. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-5-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
The usart node of the flexcom3 block is missing the DMA channels. Add it. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-4-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
Add the device tree node for the SGPIO IP block reused from the SparX-5. Keep the node disabled by default. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-3-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
The YAML binding (crypto/atmel,at91sam9g46-aes.yaml) mandates the order of the channels. Swap them to pass devicetree validation. Fixes: 290deaa1 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291") Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-2-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Michael Walle 提交于
The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: NMichael Walle <michael@walle.cc> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220420194230.3415663-1-michael@walle.ccSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Eugen Hristev 提交于
interrupt-parent is not to be used as a boolean property. It is already present in the DT in the proper way it's supposed to be used: interrupt-parent = <&gic>; This is also reported by dtbs_check: arch/arm/boot/dts/at91-sama7g5ek.dtb: interrupt-controller@e8c11000: interrupt-parent: True is not of type 'array' From schema: /.local/lib/python3.8/site-packages/dtschema/schemas/interrupts.yaml Fixes: 7540629e ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220503133127.64320-1-eugen.hristev@microchip.comSigned-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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