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  1. 25 5月, 2011 3 次提交
    • A
      mmc: sd: add support for signal voltage switch procedure · f2119df6
      由 Arindam Nath 提交于 
      Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.

Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.

If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.

Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: NArindam Nath <arindam.nath@amd.com>
Reviewed-by: NPhilip Rakity <prakity@marvell.com>
Tested-by: NPhilip Rakity <prakity@marvell.com>
Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: NChris Ball <cjb@laptop.org>
      f2119df6
    • P
      mmc: sdhci: Add pre and post reset processing for chip specific reset · 393c1a34
      由 Philip Rakity 提交于 
      Marvell pxa controllers have private registers that may need to be
modified before and after a reset is done.

For example, the SD reset operation, RESET_ALL, will reset the private
registers to their default state.  This will cause the clock adjustment
registers that may have been programmed to have incorrect values.

RESET_DATA sometimes needs to be delayed before the reset is done
(depending on SoC) to enable any transactions being handled by the
SDIO card to be completed.  Needed in pre SD 3.0 silicon to handle
clock gating.

Implement hooks to allow this to happen.
Signed-off-by: NPhilip Rakity <prakity@marvell.com>
Signed-off-by: NChris Ball <cjb@laptop.org>
      393c1a34
    • M
      mmc: sdhci: work around broken dma boundary behavior · f6a03cbf
      由 Mikko Vinni 提交于 
      Some SD host controllers (noticed on an integrated JMicron SD reader on an
HP Pavilion dv5-1250eo laptop) don't update the dma address register before
signaling a dma interrupt due to a dma boundary. Update the register
manually to the next boundary (by default 512KiB), at which the transfer
stopped.

As long as each transfer is at most 512KiB in size (guaranteed by a BUG_ON
in sdhci_prepare_data()) and the boundary is kept at the default value,
this fix is needed at most once per transfer. Smaller boundaries are taken
care of by counting the transferred bytes.

Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28462Signed-off-by: NMikko Vinni <mmvinni@yahoo.com>
Signed-off-by: NChris Ball <cjb@laptop.org>
      f6a03cbf
  3. 25 3月, 2011 1 次提交
  5. 09 1月, 2011 2 次提交
  7. 23 11月, 2010 1 次提交
  9. 08 11月, 2010 1 次提交
  11. 23 10月, 2010 6 次提交
  13. 21 8月, 2010 1 次提交
  15. 11 8月, 2010 5 次提交
  17. 28 5月, 2010 4 次提交
  19. 18 12月, 2009 1 次提交
  21. 23 9月, 2009 2 次提交
  23. 30 7月, 2009 1 次提交
    • A
      sdhci: get rid of "frequency too high" flood when using eSDHC · a9e58f25
      由 Anton Vorontsov 提交于 
      Since commit 8dfd0374 ("MMC core: limit
minimum initialization frequency to 400kHz") MMC core checks for minimum
frequency, and that causes following messages flood when using eSDHC
controllers:

  ...
  mmc0: Minimum clock frequency too high for identification mode
  mmc0: Minimum clock frequency too high for identification mode
  ...

The warnings are legitimate, since if we'd use 133 MHz clocks for standard
SDHCI controllers, we'd not able to scale frequency down to 400 kHz.

But eSDHC controllers have a non-standard SD clock management, so we can
divide clock by 256 * 16, not just 256.

This patch introduces get_min_clock() callback for sdhci core and
implements it for sdhci-of driver, and thus fixes the issue.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Cc: Matt Fleming <matt@console-pimps.org>
Cc: Ian Molton <ian@mnementh.co.uk>
Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com>
Cc: Pierre Ossman <drzeus@drzeus.cx>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      a9e58f25
  25. 22 6月, 2009 3 次提交
  27. 14 6月, 2009 1 次提交
  29. 04 5月, 2009 1 次提交
  31. 25 3月, 2009 7 次提交