- 14 11月, 2013 1 次提交
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由 Thomas Gleixner 提交于
No point in having this bit defined by architecture. Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Acked-by: NPeter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20130917183629.090698799@linutronix.de
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- 06 11月, 2013 1 次提交
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由 Michael Opdenacker 提交于
This patch removes a duplicate define from arch/mips/boot/ecoff.h Signed-off-by: NMichael Opdenacker <michael.opdenacker@free-electrons.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6081/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 05 11月, 2013 1 次提交
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由 Maciej W. Rozycki 提交于
Another whitespace clean-up, this removes tabs from between sentences in some comments. Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6103/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 31 10月, 2013 1 次提交
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由 Wei Yongjun 提交于
In case of error, the function devm_request_and_ioremap() returns NULL pointer not ERR_PTR(). Fix it by using devm_ioremap_resource() instead of devm_request_and_ioremap(). Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: NJohn Crispin <blogic@openwrt.org> Cc: grant.likely@linaro.org Cc: rob.herring@calxeda.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6098/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 10月, 2013 36 次提交
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由 Markos Chandras 提交于
The GIC interrupt offsets are calculated based on the value of NR_CPUS. However, this is wrong because NR_CPUS may or may not contain the real number of the actual cpus present in the system. We fix that by using the 'nr_cpu_ids' variable which contains the real number of cpus in the system. Previously, an MT core (eg with 8 VPEs) will fail to boot if NR_CPUS was > 8 with the following errors: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at kernel/irq/chip.c:670 __irq_set_handler+0x15c/0x164() Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.12.0-rc5-00087-gced5633 5 Stack : 00000006 00000004 00000000 00000000 00000000 00000000 807a4f36 00000053 807a0000 00000000 80173218 80565aa8 00000000 00000000 00000000 0000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000000 00000000 00000000 00000000 8054fd00 8054fd94 80500514 805657a7 8016eb4 807a0000 80500514 00000000 00000000 80565aa8 8079a5d8 80565766 8054fd0 ... Call Trace: [<801098c0>] show_stack+0x64/0x7c [<8049c6b0>] dump_stack+0x64/0x84 [<8012efc4>] warn_slowpath_common+0x84/0xb4 [<8012f00c>] warn_slowpath_null+0x18/0x24 [<80173218>] __irq_set_handler+0x15c/0x164 [<80587cf4>] arch_init_ipiirq+0x2c/0x3c [<805880c8>] arch_init_irq+0x3c4/0x4bc [<80588e28>] init_IRQ+0x3c/0x50 [<805847e8>] start_kernel+0x230/0x3d8 ---[ end trace 4eaa2a86a8e2da26 ]--- This is now fixed and the Malta board can boot with any NR_CPUS value which also helps supporting more processors in a single kernel binary. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6091/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Leonid Yegoshin 提交于
An NMI exception delivered from YAMON delivers the PC in ErrorPC instead of EPC. It's also necessary to clear the Status.BEV bit for the page fault exception handler to work properly. [ralf@linux-mips: Let the assembler do the loading of the mask value rather than the convoluted explicit %hi/%lo manual relocation sequence from the original patch.] Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6035/Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Reviewed-by: NMarkos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6084/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Leonid Yegoshin 提交于
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6023/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Deng-Cheng Zhu 提交于
The PIIX4_ICTLR* and PIIX4_OCW* defines are not used by any other files. Remove them. The only file (other than fixup-malta.c which includes piix4.h in patch #1) containing "#include <asm/mips-boards/piix4.h>" is arch/mips/mti-malta/malta-int.c whose first version is actually "1da177e4:arch/mips/mips-boards/malta/malta_int.c". In that version, in the function get_int(), things in piix4.h are used. But now malta-int.c no longer needs those stuff. Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6032/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Deng-Cheng Zhu 提交于
Make the code more readable by using defines. Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6031/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Steven J. Hill 提交于
Always register the R4K clocksource when CONFIG_CSRC_R4K is selected, regardless of selected support for other clocksources. The kernel will select the best clocksource based on their ratings, making it safe to register R4K unconditionally and use it as a fallback should the kernel be run on a system where other selected clocksources are inoperable. Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6024/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
It was ugly. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
Checking for n<0 && n>9 makes no sense because it can never be true. Moreover, we can have up to 64 vectored interrupts so BUG_ON(n>9) was wrong anyway. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Acked-by: NSteven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5909/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Nobody seems to care about this platform anymore and my attempts to find somebody willing to provide some tlc for PowerTV have failed so far. So let's nuke the bloody thing. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5910/
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Set ret just so __must_check is satisfied but don't use the variable for anything yet. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
This enables /proc/<pid>/syscall and the ptrace PTRACE_GETREGSET and PTRACE_SETREGSET operations. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
There are no users yet of task_user_regset_view. yet; users will be implemented rsp activated in subsequent commits. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
This gets us rid of the hard to maintain table of the number of syscall arguments and paves the way for further restructuring of the syscall code. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
The generic version is wrong for MIPS. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
These are a leftover of the IRIX compat code which was removed in 2957c9e6 (kernel.org) rsp. b934da913f236bca00c41d9e386e980586000461 (lmo) [[MIPS] IRIX: Goodbye and thanks for all the fish]. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
This is necessary because MIPS doesn't use HAVE_ARCH_SIGINFO_T for historical reasons. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jayachandran C 提交于
Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context to be used for saving PGD. This option was also tied to using a scratch register for storing PGD. This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 Context register in this case. The code to store the current pgd for the TLB miss handler is now generated in all cases. When scratch register is available, the PGD is also stored in the scratch register. Signed-off-by: NJayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/5906/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
There is no reliable way to tell R4000/R4400 SC and MC variations apart, however simple heuristic should give good results. Only the MC version supports coherent caching so we can rely on such a mode having been set for KSEG0 by the power-on firmware to reliably indicate an MC processor. SC processors reportedly hang on coherent cached memory accesses and Linux is linked to a cached load address so the firmware has to use the correct caching mode to download the kernel image in a cached mode successfully. OTOH if the firmware chooses to use either the non-coherent cached or the uncached mode for KSEG0 on an MC processor, then the SC variant will be reported, just as we currently do, so no regression here. Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: Jonas Gorski <jogo@openwrt.org> Cc: MIPS Mailing List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5882/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5877/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Commit 70342287 [MIPS: Whitespace cleanup.] did a lot of good and a little damage. Revert the damage. Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5875/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
This change complements commits d0da7c002f7b2a93582187a9e3f73891a01d8ee4 [MIPS: DEC: Convert to new irq_chip functions] and 5359b938 [MIPS: DECstation I/O ASIC DMA interrupt handling fix] and implements automatic handling of the two classes of DMA interrupts the I/O ASIC implements, informational and errors. Informational DMA interrupts do not stop the transfer and use the `handle_edge_irq' handler that clears the request right away so that another request may be recorded while the previous is being handled. DMA error interrupts stop the transfer and require a corrective action before DMA can be reenabled. Therefore they use the `handle_fasteoi_irq' handler that only clears the request on the way out. Because MIPS processor interrupt inputs, one of which the I/O ASIC's interrupt controller is cascaded to, are level-triggered it is recommended that error DMA interrupt action handlers are registered with the IRQF_ONESHOT flag set so that they are run with the interrupt line masked. This change removes the export of clear_ioasic_dma_irq that now does not have to be called by device drivers to clear interrupts explicitly anymore. Originally these interrupts were cleared in the .end handler of the `irq_chip' structure, before it was removed. Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5874/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Felix Fietkau 提交于
The semantics stay the same - on Cavium Octeon the functions were dead code (it overrides the MIPS DMA ops) - on other platforms they contained no code at all. Signed-off-by: NFelix Fietkau <nbd@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5720/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Yoichi Yuasa 提交于
Signed-off-by: NYoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/948/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Yoichi Yuasa 提交于
Signed-off-by: NYoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/947/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Florian Fainelli 提交于
Add support for the LZ4 compression scheme in the ZBOOT decompression stub, in order to support it we need to: - select the "lz4" compression tool to compress the vmlinux.bin payload - memcpy() is also required for decompress_unlz4.c so we share the implementation between GZIP, XZ and now LZ4 Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: james.hogan@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/5829/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Florian Fainelli 提交于
There is currently no corresponding ELF program header for the "text" loadable segment which is confusing for some bootloader out there such as CFE because it expects to find a program header matching the segment it is trying to load. The Linux kernel ELF binary "vmlinux" has a similar program header for the text segment so we just mimic this here too. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: james.hogan@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/5827/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Florian Fainelli 提交于
Add support for the XZ compression scheme in the ZBOOT decompression stub, in order to support it we need to: - select the "xzkern" compression tool to compress the vmlinux.bin payload - link with ashldi3.o for xz_dec_run() to work - memcpy() is also required for decompress_unxz.c so we share the implementation between GZIP and XZ Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: james.hogan@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/5818/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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