- Add DT and driver support for SC8280XP/SA8540P basic interconnects where
  interconnect bandwidth must be requested before enabling interconnect
  clocks (Johan Hovold)

- Add 'dma-coherent' property (Johan Hovold)

* remotes/lorenzo/pci/qcom:
  dt-bindings: PCI: qcom: Allow 'dma-coherent' property
  PCI: qcom: Add basic interconnect support
  dt-bindings: PCI: qcom: Add SC8280XP/SA8540P interconnects

- Add sentinel to mt7621_pcie_quirks_match[] to prevent oops when parsing
  the table (John Thomson)

* remotes/lorenzo/pci/mt7621:
  PCI: mt7621: Add sentinel to quirks table

- Add a .release() callback for the Endpoint Controller library so an
  Endpoint driver is removable (Yoshihiro Shimoda)

- Fix pci-epf-vntb kernel-doc and whitespace (Frank Li)

- Fix pci-epf-vntb error path usage of pci_epc_mem_free_addr() (Frank Li)

- Remove pci-epf-vntb unused epf_db_phy (Frank Li)

- Fix pci-epf-vntb sparse warnings (Frank Li)

* remotes/lorenzo/pci/endpoint:
  PCI: endpoint: pci-epf-vntb: Fix sparse ntb->reg build warning
  PCI: endpoint: pci-epf-vntb: Fix sparse build warning for epf_db
  PCI: endpoint: pci-epf-vntb: Replace hardcoded 4 with sizeof(u32)
  PCI: endpoint: pci-epf-vntb: Remove unused epf_db_phy struct member
  PCI: endpoint: pci-epf-vntb: Fix call pci_epc_mem_free_addr() in error path
  PCI: endpoint: pci-epf-vntb: Fix struct epf_ntb_ctrl indentation
  PCI: endpoint: pci-epf-vntb: Clean up kernel_doc warning
  PCI: endpoint: Fix WARN() when an endpoint driver is removed

- Fix n_fts[] array overrun (Vidya Sagar)

- Don't advertise PTM Responder role for Endpoints (Vidya Sagar)

- Fix qcom "reset assert" error message (Manivannan Sadhasivam)

- Downgrade "link didn't come up" message to dev_info (Vidya Sagar)

- Initialize PHY before deasserting core reset so the link comes up on
  boards where the PHY provides the reference clock (this was a regression
  in v6.0) (Sascha Hauer)

- Switch histb to the gpiod API (Dmitry Torokhov)

- Fix imx6sx and imx8mq clock names in DT binding (Serge Semin)

- Fix visconti MSI interrupt in DT binding (Serge Semin)

- Consolidate reset-gpio, cdm, windows info in common DT shared by both
  Root Port and Endpoint bindings (Serge Semin)

- Remove bus node from DT examples (Serge Semin)

- Add common phys, phy-names to DT (Serge Semin)

- Add default max-link-speed of Gen5 to DT (Serge Semin)

- Apply generic schema for generic device  (Serge Semin)

- Add default max-functions of 32 to DT (Serge Semin)

- Add common interrupts, interrupt-names to DT (Serge Semin)

- Add common regs, reg-names to DT (Serge Semin)

- Add common clocks, resets to DT (Serge Semin)

- Add dma-coherent to DT (Serge Semin)

- Apply common schema to Rockchip DT (Serge Semin)

- Add Baikal-T1 DT bindings (Serge Semin)

- Add dma-ranges support in DesignWare core (Serge Semin)

- Add dw_pcie_cap_is() for testing controller capabilities (Serge Semin)

- Add generic resources getter to DesignWare core (Serge Semin)

- Combine iATU detection procedures (Serge Semin)

- Add generic clock and reset names to DesignWare core (Serge Semin)

- Add Baikal-T1 PCIe controller driver (Serge Semin)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Add Baikal-T1 PCIe controller support
  PCI: dwc: Introduce generic platform clocks and resets
  PCI: dwc: Combine iATU detection procedures
  PCI: dwc: Introduce generic resources getter
  PCI: dwc: Introduce generic controller capabilities interface
  PCI: dwc: Introduce dma-ranges property support for RC-host
  dt-bindings: PCI: dwc: Add Baikal-T1 PCIe Root Port bindings
  dt-bindings: PCI: dwc: Apply common schema to Rockchip DW PCIe nodes
  dt-bindings: PCI: dwc: Add dma-coherent property
  dt-bindings: PCI: dwc: Add clocks/resets common properties
  dt-bindings: PCI: dwc: Add reg/reg-names common properties
  dt-bindings: PCI: dwc: Add interrupts/interrupt-names common properties
  dt-bindings: PCI: dwc: Add max-functions EP property
  dt-bindings: PCI: dwc: Apply generic schema for generic device only
  dt-bindings: PCI: dwc: Add max-link-speed common property
  dt-bindings: PCI: dwc: Add phys/phy-names common properties
  dt-bindings: PCI: dwc: Remove bus node from the examples
  dt-bindings: PCI: dwc: Detach common RP/EP DT bindings
  dt-bindings: visconti-pcie: Fix interrupts array max constraints
  dt-bindings: imx6q-pcie: Fix clock names for imx6sx and imx8mq
  PCI: histb: Switch to using gpiod API
  PCI: imx6: Initialize PHY before deasserting core reset
  PCI: dwc: Use dev_info for PCIe link down event logging
  PCI: qcom: Fix error message for reset_control_assert()
  PCI: designware-ep: Disable PTM capabilities for EP mode
  PCI: Add PCI_PTM_CAP_RES macro
  PCI: dwc: Fix n_fts[] array overrun

- Enable Multi-MSI (Jim Quinlan)

- Wait for 100ms after PERST# deassert for power and clocks to stabilize
  (Jim Quinlan)

- Use readl_poll_timeout_atomic() instead of hand-rolled timeout loop (Jim
  Quinlan)

- Drop needless "inline" annotations (Jim Quinlan)

- Set RCB_MPS mode bit so data for reads up to MPS are returned in a single
  completion (Jim Quinlan)

* remotes/lorenzo/pci/brcmstb:
  PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits
  PCI: brcmstb: Drop needless 'inline' annotations
  PCI: brcmstb: Replace status loops with read_poll_timeout_atomic()
  PCI: brcmstb: Wait for 100ms following PERST# deassert
  PCI: brcmstb: Enable Multi-MSI

- Add ti,j721e-pci-host interrupt controller definition (Matt Ranostay)

- Add ti,j721e-pci-host interrupt properties (Matt Ranostay)

- Add ti,j721s2 host mode device-id (Matt Ranostay)

- Add mediatek-gen3 iommu, power properties (Jianjun Wang)

- Add mediatek-gen3 SoC-based clock names (Frank Wunderlich)

- Add mediatek-gen3 mt7986 support (Frank Wunderlich)

* remotes/lorenzo/pci/dt:
  dt-bindings: PCI: mediatek-gen3: add support for mt7986
  dt-bindings: PCI: mediatek-gen3: add SoC based clock config
  dt-bindings: PCI: Add host mode device-id for j721s2 platform
  dt-bindings: PCI: mediatek-gen3: Support mt8195
  dt-bindings: PCI: ti,j721e-pci-*: Add missing interrupt properties
  dt-bindings: PCI: ti,j721e-pci-host: add interrupt controller definition

- Fix a double free in the error path of creating sysfs "resource%d"
  attributes (Sascha Hauer)

* pci/sysfs:
  PCI/sysfs: Fix double free in error path

- Remove EfiMemoryMappedIO regions from the E820 map to allow PCI core to
  allocate BARs from them.  The only purpose of EfiMemoryMappedIO is to
  tell the OS to map things needed by EFI runtime services, so it's often
  used for PCI host bridge apertures.  If we can't allocate from those
  apertures, we can't hot-add devices (Bjorn Helgaas)

* pci/resource:
  x86/PCI: Use pr_info() when possible
  x86/PCI: Fix log message typo
  x86/PCI: Tidy E820 removal messages
  PCI: Skip allocate_resource() if too little space available
  efi/x86: Remove EfiMemoryMappedIO from E820 map

- Squash portdrv_core.c and portdrv_pci.c into portdrv.c to make it easier
  to find things (Bjorn Helgaas)

- Allow AER service only for Root Ports & RCECs so portdrv can successfully
  bind to other devices that have AER but lack MSI (which they don't need
  for AER), which allows power management for those devices (Bjorn Helgaas)

* pci/portdrv:
  PCI/portdrv: Allow AER service only for Root Ports & RCECs
  PCI/portdrv: Unexport pcie_port_service_register(), pcie_port_service_unregister()
  PCI/portdrv: Move private things to portdrv.c
  PCI/portdrv: Squash into portdrv.c

- Convert AGP efficeon, intel, amd-k7, ati, nvidia to generic power
  management (Bjorn Helgaas)

* pci/pm-agp:
  agp/via: Update to DEFINE_SIMPLE_DEV_PM_OPS()
  agp/sis: Update to DEFINE_SIMPLE_DEV_PM_OPS()
  agp/amd64: Update to DEFINE_SIMPLE_DEV_PM_OPS()
  agp/nvidia: Convert to generic power management
  agp/ati: Convert to generic power management
  agp/amd-k7: Convert to generic power management
  agp/intel: Convert to generic power management
  agp/efficeon: Convert to generic power management

- Remove unused 'state' parameter to pci_legacy_suspend_late() (Bjorn
  Helgaas)

* pci/pm:
  PCI/PM: Remove unused 'state' parameter to pci_legacy_suspend_late()

- Use METHOD_NAME__UID instead of plain string to make it easier to find
  all uses (Yipeng Zou)

* pci/misc:
  PCI/ACPI: Use METHOD_NAME__UID instead of plain string

- Enable pciehp by default if USB4 is enabled because USB4/Thunderbolt
  tunneling depends on native PCIe hotplug (Albert Zhou)

- Make sure pciehp binds only to Downstream Ports, not Upstream Ports
  (Rafael J. Wysocki)

- Remove unused get_mode1_ECC_cap callback in shpchp (Ian Cowan)

- Enable pciehp Command Completed Interrupt only if supported to reduce
  confusion when looking at lspci output (Pali Rohár)

* pci/hotplug:
  PCI: pciehp: Enable Command Completed Interrupt only if supported
  PCI: shpchp: Remove unused get_mode1_ECC_cap callback
  PCI: acpiphp: Avoid setting is_hotplug_bridge for PCIe Upstream Ports
  PCI/portdrv: Set PCIE_PORT_SERVICE_HP for Root and Downstream Ports only
  PCI: pciehp: Enable by default if USB4 enabled

- Only read/write PCIe Link 2 registers for devices with Links and PCIe
  Capability version >= 2 (Maciej W. Rozycki)

- Revert a patch that cleared PCI_STATUS during enumeration because it
  broke Linux guests on Apple's virtualization framework (Bjorn Helgaas)

- Assign PCI domain IDs using IDAs so IDs can be easily reused after
  loading/unloading host bridge drivers (Pali Rohár)

- Fix pci_device_is_present(), which previously always returned "false" for
  VFs because their vendor ID is always 0xfff (Michael S. Tsirkin)

- Check for alloc failure in pci_request_irq() (Zeng Heng)

* pci/enumeration:
  PCI: Check for alloc failure in pci_request_irq()
  PCI: Fix pci_device_is_present() for VFs by checking PF
  PCI: Assign PCI domain IDs by ida_alloc()
  Revert "PCI: Clear PCI_STATUS when setting up device"
  PCI: Access Link 2 registers only for devices with Links

- Fix calculation of DOE length to account for the "0 means 2^18 DWORDs"
  special case (Li Ming)

* pci/doe:
  PCI/DOE: Fix maximum data object length miscalculation

Use pr_info() and similar when possible.  No functional change intended.

Link: https://lore.kernel.org/r/20221209205131.GA1726524@bhelgaasSuggested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>

Add missing word in the log message:

  - ... so future kernels can this automatically
  + ... so future kernels can do this automatically
Suggested-by: NAndy Shevchenko <andriy.shevchenko@intel.com>
Link: https://lore.kernel.org/r/20221208190341.1560157-5-helgaas@kernel.orgSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

These messages:

  clipped [mem size 0x00000000 64bit] to [mem size 0xfffffffffffa0000 64bit] for e820 entry [mem 0x0009f000-0x000fffff]

aren't as useful as they could be because (a) the resource is often
IORESOURCE_UNSET, so we print the size instead of the start/end and (b) we
print the available resource even if it is empty after removing the E820
entry.

Print the available space by hand to avoid the IORESOURCE_UNSET problem and
only if it's non-empty.  No functional change intended.

Link: https://lore.kernel.org/r/20221208190341.1560157-4-helgaas@kernel.orgSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

pci_bus_alloc_from_region() allocates MMIO space by iterating through all
the resources available on the bus.  The available resource might be
reduced if the caller requires 32-bit space or we're avoiding BIOS or E820
areas.

Don't bother calling allocate_resource() if we need more space than is
available in this resource.  This prevents some pointless and annoying
messages about avoided areas.

Link: https://lore.kernel.org/r/20221208190341.1560157-3-helgaas@kernel.orgSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Firmware can use EfiMemoryMappedIO to request that MMIO regions be mapped
by the OS so they can be accessed by EFI runtime services, but should have
no other significance to the OS (UEFI r2.10, sec 7.2).  However, most
bootloaders and EFI stubs convert EfiMemoryMappedIO regions to
E820_TYPE_RESERVED entries, which prevent Linux from allocating space from
them (see remove_e820_regions()).

Some platforms use EfiMemoryMappedIO entries for PCI MMCONFIG space and PCI
host bridge windows, which means Linux can't allocate BAR space for
hot-added devices.

Remove large EfiMemoryMappedIO regions from the E820 map to avoid this
problem.

Leave small (< 256KB) EfiMemoryMappedIO regions alone because on some
platforms, these describe non-window space that's included in host bridge
_CRS.  If we assign that space to PCI devices, they don't work.  On the
Lenovo X1 Carbon, this leads to suspend/resume failures.

The previous solution to the problem of allocating BARs in these regions
was to add pci_crs_quirks[] entries to disable E820 checking for these
machines (see d341838d ("x86/PCI: Disable E820 reserved region clipping
via quirks")):

  Acer   DMI_PRODUCT_NAME    Spin SP513-54N
  Clevo  DMI_BOARD_NAME      X170KM-G
  Lenovo DMI_PRODUCT_VERSION *IIL*

Florent reported the BAR allocation issue on the Clevo NL4XLU.  We could
add another quirk for the NL4XLU, but I hope this generic change can solve
it for many machines without having to add quirks.

This change has been tested on Clevo X170KM-G (Konrad) and Lenovo Ideapad
Slim 3 (Matt) and solves the problem even when overriding the existing
quirks by booting with "pci=use_e820".

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216565     Clevo NL4XLU
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206459#c78 Clevo X170KM-G
Link: https://bugzilla.redhat.com/show_bug.cgi?id=1868899    Ideapad Slim 3
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2029207    X1 Carbon
Link: https://lore.kernel.org/r/20221208190341.1560157-2-helgaas@kernel.orgReported-by: NFlorent DELAHAYE <kernelorg@undead.fr>
Tested-by: NKonrad J Hambrick <kjhambrick@gmail.com>
Tested-by: NMatt Hansen <2lprbe78@duck.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Previously portdrv allowed the AER service for any device with an AER
capability (assuming Linux had control of AER) even though the AER service
driver only attaches to Root Port and RCECs.

Because get_port_device_capability() included AER for non-RP, non-RCEC
devices, we tried to initialize the AER IRQ even though these devices
don't generate AER interrupts.

Intel DG1 and DG2 discrete graphics cards contain a switch leading to a
GPU.  The switch supports AER but not MSI, so initializing an AER IRQ
failed, and portdrv failed to claim the switch port at all.  The GPU itself
could be suspended, but the switch could not be put in a low-power state
because it had no driver.

Don't allow the AER service on non-Root Port, non-Root Complex Event
Collector devices.  This means we won't enable Bus Mastering if the device
doesn't require MSI, the AER service will not appear in sysfs, and the AER
service driver will not bind to the device.

Link: https://lore.kernel.org/r/20221207084105.84947-1-mika.westerberg@linux.intel.com
Link: https://lore.kernel.org/r/20221210002922.1749403-1-helgaas@kernel.orgBased-on-patch-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

The No Command Completed Support bit in the Slot Capabilities register
indicates whether Command Completed Interrupt Enable is unsupported.

We already check whether No Command Completed Support bit is set in
pcie_wait_cmd(), and do not wait in this case.

Don't enable this Command Completed Interrupt at all if NCCS is set, so
that when users dump configuration space from userspace, the dump does not
confuse them by saying that Command Completed Interrupt is not supported,
but it is enabled.

Link: https://lore.kernel.org/r/20220927141926.8895-2-kabel@kernel.orgSigned-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NMarek Behún <kabel@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLukas Wunner <lukas@wunner.de>

Add compatible string and clock-definition for mt7986. It needs 4 clocks
for PCIe, define them in binding.

Link: https://lore.kernel.org/r/20221127114142.156573-5-linux@fw-web.deSigned-off-by: NFrank Wunderlich <frank-w@public-files.de>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NJianjun Wang <jianjun.wang@mediatek.com>

The PCIe driver covers different SOC which needing different clock
configs. Define them based on compatible.

Link: https://lore.kernel.org/r/20221127114142.156573-4-linux@fw-web.deSigned-off-by: NFrank Wunderlich <frank-w@public-files.de>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NJianjun Wang <jianjun.wang@mediatek.com>

Devices on some PCIe buses may be cache coherent and must be marked as
such in the devicetree to avoid data corruption.

This is specifically needed on recent Qualcomm platforms like SC8280XP.

Link: https://lore.kernel.org/r/20221205094530.12883-1-johan+linaro@kernel.orgSigned-off-by: NJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>

Current driver is missing a sentinel in the struct soc_device_attribute
array, which causes an oops when assessed by the
soc_device_match(mt7621_pcie_quirks_match) call.

This was only exposed once the CONFIG_SOC_MT7621 mt7621 soc_dev_attr
was fixed to register the SOC as a device, in:

commit 7c18b64b ("mips: ralink: mt7621: do not use kzalloc too early")

Fix it by adding the required sentinel.

Link: https://lore.kernel.org/lkml/26ebbed1-0fe9-4af9-8466-65f841d0b382@app.fastmail.com
Link: https://lore.kernel.org/r/20221205204645.301301-1-git@johnthomson.fastmail.com.au
Fixes: b483b4e4 ("staging: mt7621-pci: add quirks for 'E2' revision using 'soc_device_attribute'")
Signed-off-by: NJohn Thomson <git@johnthomson.fastmail.com.au>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NSergio Paracuellos <sergio.paracuellos@gmail.com>

  pci-epf-vntb.c:1128:33: sparse:     expected void [noderef] __iomem *base
  pci-epf-vntb.c:1128:33: sparse:     got struct epf_ntb_ctrl *reg

Add __iomem type cast in vntb_epf_peer_spad_read() and
vntb_epf_peer_spad_write().

Link: https://lore.kernel.org/r/20221102141014.1025893-8-Frank.Li@nxp.comReported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NFrank Li <frank.li@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NManivannan Sadhasivam <mani@kernel.org>

Use epf_db[i] dereference instead of readl() because epf_db is
in memory allocated by dma_alloc_coherent(), not I/O.

Remove useless/duplicated readl() in the process.

Link: https://lore.kernel.org/r/20221102141014.1025893-7-Frank.Li@nxp.comSigned-off-by: NFrank Li <frank.li@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

NTB spad entry item size is sizeof(u32), replace hardcoded 4 with it.

Link: https://lore.kernel.org/r/20221102141014.1025893-6-Frank.Li@nxp.comSigned-off-by: NFrank Li <frank.li@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NManivannan Sadhasivam <mani@kernel.org>

epf_db_phy member in struct epf_ntb is not used, remove it.

Link: https://lore.kernel.org/r/20221102141014.1025893-5-Frank.Li@nxp.comSigned-off-by: NFrank Li <frank.li@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NManivannan Sadhasivam <mani@kernel.org>

Replace pci_epc_mem_free_addr() with pci_epf_free_space() in the
error handle path to match pci_epf_alloc_space().

Link: https://lore.kernel.org/r/20221102141014.1025893-4-Frank.Li@nxp.com
Fixes: e35f56bb ("PCI: endpoint: Support NTB transfer between RC and EP")
Signed-off-by: NFrank Li <frank.li@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Align the indentation of struct epf_ntb_ctrl with other structs in
the driver.

Link: https://lore.kernel.org/r/20221102141014.1025893-3-Frank.Li@nxp.comSigned-off-by: NFrank Li <frank.li@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Cleanup warning found by scripts/kernel-doc.

Consolidate terms:

- host, host1 to HOST
- vhost, vHost, Vhost, VHOST2 to VHOST

Link: https://lore.kernel.org/r/20221102141014.1025893-2-Frank.Li@nxp.comSigned-off-by: NFrank Li <frank.li@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NManivannan Sadhasivam <mani@kernel.org>

Baikal-T1 SoC is equipped with DWC PCIe v4.60a host controller. It can be
trained to work up to Gen.3 speed over up to x4 lanes. The host controller
is attached to the DW PCIe 3.0 PCS via the PIPE-4 interface, which in its
turn is connected to the DWC 10G PHY. The whole system is supposed to be
fed up with four clock sources: DBI peripheral clock, AXI application
clocks and external PHY/core reference clock generating the 100MHz signal.
In addition to that the platform provide a way to reset each part of the
controller: sticky/non-sticky bits, host controller core, PIPE interface,
PCS/PHY and Hot/Power reset signal. The driver also provides a way to
handle the GPIO-based PERST# signal.

Note due to the Baikal-T1 MMIO peculiarity we have to implement the DBI
interface accessors which make sure the IO operations are dword-aligned.

Link: https://lore.kernel.org/r/20221113191301.5526-21-Sergey.Semin@baikalelectronics.ruSigned-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Currently almost each platform driver uses its own resets and clocks
naming in order to get the corresponding descriptors. It makes the code
harder to maintain and comprehend especially seeing the DWC PCIe core main
resets and clocks signals set hasn't changed much for about at least one
major IP-core release. So in order to organize things around these signals
we suggest to create a generic interface for them in accordance with the
naming introduced in the DWC PCIe IP-core reference manual:

Application clocks:
- "dbi"  - data bus interface clock (on some DWC PCIe platforms it's
           referred as "pclk", "pcie", "sys", "ahb", "cfg", "iface",
           "gio", "reg", "pcie_apb_sys");
- "mstr" - AXI-bus master interface clock (some DWC PCIe glue drivers
           refer to this clock as "port", "bus", "pcie_bus",
           "bus_master/master_bus/axi_m", "pcie_aclk");
- "slv"  - AXI-bus slave interface clock (also called as "port", "bus",
           "pcie_bus", "bus_slave/slave_bus/axi_s", "pcie_aclk",
           "pcie_inbound_axi").

Core clocks:
- "pipe" - core-PCS PIPE interface clock coming from external PHY (it's
           normally named by the platform drivers as just "pipe");
- "core" - primary clock of the controller (none of the platform drivers
           declare such a clock but in accordance with the ref. manual
           the devices may have it separately specified);
- "aux"  - auxiliary PMC domain clock (it is named by some platforms as
           "pcie_aux" and just "aux");
- "ref"  - Generic reference clock (it is a generic clock source, which
           can be used as a signal source for multiple interfaces, some
           platforms call it as "ref", "general", "pcie_phy",
           "pcie_phy_ref").

Application resets:
- "dbi"  - Data-bus interface reset (it's CSR interface clock and is
           normally called as "apb" though technically it's not APB but
           DWC PCIe-specific interface);
- "mstr" - AXI-bus master reset (some platforms call it as "port", "apps",
           "bus", "axi_m");
- "slv"  - ABI-bus slave reset (some platforms call it as "port", "apps",
           "bus", "axi_s").

Core resets:
- "non-sticky" - non-sticky CSR flags reset;
- "sticky"     - sticky CSR flags reset;
- "pipe"       - PIPE-interface (Core-PCS) logic reset (some platforms
                 call it just "pipe");
- "core"       - controller primary reset (resets everything except PMC
                 module, some platforms refer to this signal as "soft",
                 "pci");
- "phy"        - PCS/PHY block reset (strictly speaking it is normally
                 connected to the input of an external block, but the
                 reference manual says it must be available for the PMC
                 working correctly, some existing platforms call it
                 "pciephy", "phy", "link");
- "hot"        - PMC hot reset signal (also called as "sleep");
- "pwr"        - cold reset signal (can be referred as "pwr", "turnoff").

Bus reset:
- "perst" - PCIe standard signal used to reset the PCIe peripheral
            devices.

As you can see each platform uses it's own naming for basically the same
set of the signals. In the framework of this commit we suggest to add a
set of the clocks and reset signals resources, corresponding names and
identifiers for each denoted entity. At current stage the platforms will
be able to use the provided infrastructure to automatically request all
these resources and manipulate with them in the Host/EP init callbacks.
Alas it isn't that easy to create a common cold/hot reset procedure due to
too many platform-specifics in the procedure, like the external flags
exposure and the delays requirement.

Link: https://lore.kernel.org/r/20221113191301.5526-20-Sergey.Semin@baikalelectronics.ruSigned-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Since the iATU CSR region is now retrieved in the DW PCIe resources getter
there is no much benefits in the iATU detection procedures splitting up.
Therefore let's join the iATU unroll/viewport detection procedure with the
rest of the iATU parameters detection code. The resultant method will be
as coherent as before, while the redundant functions will be eliminated
thus producing more readable code.

Link: https://lore.kernel.org/r/20221113191301.5526-19-Sergey.Semin@baikalelectronics.ruSigned-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Currently the DW PCIe Root Port and Endpoint CSR spaces are retrieved in
the separate parts of the DW PCIe core driver. It doesn't really make
sense since the both controller types have identical set of the core CSR
regions: DBI, DBI CS2 and iATU/eDMA. Thus we can simplify the DW PCIe Host
and EP initialization methods by moving the platform-specific registers
space getting and mapping into a common method. It gets to be even more
justified seeing the CSRs base address pointers are preserved in the
common DW PCIe descriptor. Note all the OF-based common DW PCIe settings
initialization will be moved to the new method too in order to have a
single function for all the generic platform properties handling in single
place.

A nice side-effect of this change is that the pcie-designware-host.c and
pcie-designware-ep.c drivers are cleaned up from all the direct dw_pcie
storage modification, which makes the DW PCIe core, Root Port and Endpoint
modules more coherent.

Link: https://lore.kernel.org/r/20221113191301.5526-18-Sergey.Semin@baikalelectronics.ruSigned-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>

Since in addition to the already available iATU unrolled mapping we are
about to add a few more DW PCIe platform-specific capabilities (CDM-check
and generic clocks/resets resources) let's add a generic interface to set
and get the flags indicating their availability. The new interface shall
improve maintainability of the platform-specific code.

Link: https://lore.kernel.org/r/20221113191301.5526-17-Sergey.Semin@baikalelectronics.ruSigned-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

In accordance with the generic PCIe Root Port DT-bindings the "dma-ranges"
property has the same format as the "ranges" property. The only difference
is in their semantics. The "dma-ranges" property describes the PCIe-to-CPU
memory mapping in opposite to the CPU-to-PCIe mapping of the "ranges"
property. Even though the DW PCIe controllers are normally equipped with
the internal Address Translation Unit which inbound and outbound tables
can be used to implement both properties semantics, it was surprising for
me to discover that the host-related part of the DW PCIe driver currently
supports the "ranges" property only while the "dma-ranges" windows are
just ignored. Having the "dma-ranges" supported in the driver would be
very handy for the platforms, that don't tolerate the 1:1 CPU-PCIe memory
mapping and require a customized PCIe memory layout. So let's fix that by
introducing the "dma-ranges" property support.

First of all we suggest to rename the dw_pcie_prog_inbound_atu() method to
dw_pcie_prog_ep_inbound_atu() and create a new version of the
dw_pcie_prog_inbound_atu() function. Thus we'll have two methods for the
RC and EP controllers respectively in the same way as it has been
developed for the outbound ATU setup methods.

Secondly aside with the memory window index and type the new
dw_pcie_prog_inbound_atu() function will accept CPU address, PCIe address
and size as its arguments. These parameters define the PCIe and CPU memory
ranges which will be used to setup the respective inbound ATU mapping. The
passed parameters need to be verified against the ATU ranges constraints
in the same way as it is done for the outbound ranges.

Finally the DMA-ranges detected for the PCIe controller need to be
converted to the inbound ATU entries during the host controller
initialization procedure. It will be done in the framework of the
dw_pcie_iatu_setup() method. Note before setting the inbound ranges up we
need to disable all the inbound ATU entries in order to prevent unexpected
PCIe TLPs translations defined by some third party software like
bootloaders.

Link: https://lore.kernel.org/r/20221113191301.5526-16-Sergey.Semin@baikalelectronics.ruSigned-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Baikal-T1 SoC is equipped with DWC PCIe v4.60a Root Port controller, which
link can be trained to work on up to Gen.3 speed over up to x4 lanes. The
controller is supposed to be fed up with four clock sources: DBI
peripheral clock, AXI application Tx/Rx clocks and external PHY/core
reference clock generating the 100MHz signal. In addition to that the
platform provide a way to reset each part of the controller:
sticky/non-sticky bits, host controller core, PIPE interface, PCS/PHY and
Hot/Power reset signal. The Root Port controller is equipped with multiple
IRQ lines like MSI, system AER, PME, HP, Bandwidth change, Link
equalization request and eDMA ones. The registers space is accessed over
the DBI interface. There can be no more than four inbound or outbound iATU
windows configured.

Link: https://lore.kernel.org/r/20221113191301.5526-15-Sergey.Semin@baikalelectronics.ruSigned-off-by: NSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>