Add hwmod data for RTC
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NSebastian Andrzej Siewior <sebastian@breakpoint.cc>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Tested-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Tested-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This module is needed for the SATA and PCIe PHYs.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Tested-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

DMA interrupts are now available in of, and the definitions are
duplicates in hwmod. This prevents us from dynamically allocating
interrupt resources for dma from devicetree.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

we have currently 2 DMA drivers that try to co-exist.
drivers/dma/omap-dma.c which registers it's own IRQ and is device tree
aware and uses arch/arm/plat-omap/dma.c instance created by
arch/arm/mach-omap2/dma.c to maintain channel usage (omap_request_dma).

Currently both try to register interrupts and mach-omap2/plat-omap dma.c
attempts to use the IRQ number registered by hwmod to register it's own
interrupt handler.

Now, there is no reasonable way of static allocating DMA irq in GIC
SPI when we use crossbar. However, since the dma_chan structure is
freed as a result of IRQ not being present due to devm allocation,
maintaining information of channel by platform code fails at a later
point in time when that region of memory is reused.

So, if hwmod does not indicate an IRQ number, then, assume that
dma-engine will take care of the interrupt handling.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Instead, copy the used constants from the header file to the source file.
This allows the code to be migrated under drivers folder where we don't
have access to the OMAP specific header files.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Some of the machine specific header includes are no longer used, so remove
these from the source file. This allows migration of the file under clock
driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Some of the machine specific header includes are no longer used, so remove
these from the source file. This allows migration of the file under clock
driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Helps to get rid of some runtime cpu_is_x checks. This also allows eventual
migration of the code under clock driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Currently DPLL code uses runtime cpu_is_343x checks to see if the DPLL
has freqsel fields in its control register or not. Instead, add a new
flag to the clk_features.flags and use this during runtime. Allows
eventual move of the DPLL code under clock driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses
clk_features data provided during boot. This avoids the need to use
cpu_is_X type checks runtime, and allows us to eventually move the
clock code under the clock driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Currently, same functionality is copy pasted in two locations. Instead,
add a private API for this and get rid of some duplicated code.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

These are SoC specific and get their init values based on the SoC type.
Previously the values were hard coded within the DPLL clock code, but
having them inside the clock features avoids runtime cpu_is_X type checks.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This shall be used to replace the cpu type checks around the clock code.
Actual bit values will be introduced in patches later.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Instead, copy the used bitfield definitions to the source file. Done in
preparation to migrate the clock implementation under clock driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

These are unnecessary, as the clock code is only used on OMAP4+ platforms
through clock registrations. This also allows to eventually migrate the
clock type implementation under clock driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The legacy-style definition of the hwmod addr space is no longer
required as AM33xx/AM43xx are DT-boot only, and the minimal mailbox
DT nodes have been added, so clean up this data.
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The legacy-style definition of the hwmod addr space is no longer
required after the addition of the OMAP4 mailbox DT node, so
clean up this data.

Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <bcousson@baylibre.com>
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

OMAP2 devices are devicetree boot only, and the legacy mode
of mailbox device creation should no longer be used, so remove
the mailbox attribute data and the hwmod addr space used for
creating mailboxes in legacy mode.
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The legacy platform device for mailbox should not be created for
a DT boot, so adjust the platform device initialization logic
appropriately.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add the hwmod data for the 13 instances of the system mailbox
IP in DRA7 SoC. The patch is needed for performing a soft-reset
while configuring the respective mailbox instance, otherwise is
a non-essential change for functionality. The modules are smart
idled on reset, and the IP module mode is hardware controlled.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This clock type declaration is no longer used as all omap4+ SoC clock
data has been moved to DT, thus remove it.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The mach-omap2 directory contains full register defines for OMAP4
control module but only around 27 of those are used. There are is
a total of 1795 register defines in four files with only 27 in use.
That is pretty low usefulness ratio...

I guess alot more was used when we had omap4 board files and
mach-omap2 contained more drivers but this has now changed.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
[tony@atomide.com: updated to apply]
Signed-off-by: NTony Lindgren <tony@atomide.com>

This code is not working currently and it can be removed. There is a
conflict in sharing resources with the actual HDMI driver and with
the ASoC HDMI audio DAI driver.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Currently, child nodes of the gpmc node are iterated and probed
regardless of their 'status' property. This means adding 'status =
"disabled";' has no effect.

This patch changes the iteration to only probe nodes marked as
available.
Signed-off-by: NGuido Martínez <guido@vanguardiasur.com.ar>
Tested-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The DSP platform device for TI DSP/Bridge is currently
created unconditionally whenever CONFIG_TIDSPBRIDGE is
enabled. This device should only be created on OMAP34xx/
OMAP36xx SoCs, and not for other OMAP3 derived SoCs or when
booting multi-arch images on other SoCs. So, add a check for
the SoC family both before creating the device and allocating
the carveout memory for the device.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

omap44xx_restart is defined as a static void inline when DRA7/AM437X is
defined alone, which implies that the restart function is no longer
functional even though it is built in. So, fix the definition of the
same.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The divider value provided to the _dpll_test_fint can reach value of
256 with J type DPLLs (USB etc.), which causes an overflow with the u8
datatype. Fix this by changing the parameter to be an int instead.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
[paul@pwsan.com: changed type of 'n' to unsigned int]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add the sysconfig class bits for the Super Speed USB
controllers
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Tested-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Get rid of optional clock as that is now managed by the
AHCI platform driver.

Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Tested-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The commit 7be914f2 {ARM: OMAP3: PRM/CM: Cleanup unused header} removed
some of the macros used by the TI DSP/Bridge driver. This fixes the
following build errors when trying to build DSP/Bridge driver (disabled
at present), otherwise results in the following build errors:

drivers/staging/tidspbridge/core/tiomap3430.c:531:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430.c:531:31: note: each undeclared identifier is reported only once for each function it appears in
make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430.o] Error 1
make[3]: *** Waiting for unfinished jobs....
drivers/staging/tidspbridge/core/tiomap_io.c: In function 'sm_interrupt_dsp':
drivers/staging/tidspbridge/core/tiomap_io.c:404:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap_io.c:404:31: note: each undeclared identifier is reported only once for each function it appears in
drivers/staging/tidspbridge/core/tiomap_io.c:414:12: error: 'OMAP3430_IVA2_DPLL_FREQSEL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap_io.c:415:12: error: 'OMAP3430_EN_IVA2_DPLL_SHIFT' undeclared (first use in this function)
make[3]: *** [drivers/staging/tidspbridge/core/tiomap_io.o] Error 1
drivers/staging/tidspbridge/core/tiomap3430_pwr.c: In function 'dsp_clk_wakeup_event_ctrl':
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: error: 'OMAP3430_GRPSEL_GPT5_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: note: each undeclared identifier is reported only once for each function it appears in
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:455:19: error: 'OMAP3430_GRPSEL_GPT6_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:468:19: error: 'OMAP3430_GRPSEL_GPT7_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:481:19: error: 'OMAP3430_GRPSEL_GPT8_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:494:19: error: 'OMAP3430_GRPSEL_MCBSP1_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:546:19: error: 'OMAP3430_GRPSEL_MCBSP5_MASK' undeclared (first use in this function)
make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430_pwr.o] Error 1
make[2]: *** [drivers/staging/tidspbridge] Error 2

Fixes: 7be914f2 (ARM: OMAP3: PRM/CM: Cleanup unused header)
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add DSS hwmod data for AM43xx.
Signed-off-by: NSathya Prakash M R <sathyap@ti.com>
[tomi.valkeinen@ti.com: added missing dispc flags]
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Tested-by: Felipe Balbi <balbi@ti.com> # on linux-next 5f295cdf5c5d
[paul@pwsan.com: fixed build break on AM43xx-only config]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Control module related PM initializations are now moved within control
module driver. Done in preparation to isolate the code to its own driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Done in preparation to move PRM into its own driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>

This patch moves the functionality from PM core to control driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Helps to isolate the PRM driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>

This helps to isolate the PRM into its own driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>

This isolates the PRM register access within the PRM driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>