- 23 9月, 2014 3 次提交
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由 Michel Dänzer 提交于
This might decrease the chance of IH ring buffer overflows. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michel Dänzer 提交于
Use the same format for all ring indices, and fix the calculation of the post-overflow RPTR. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michel Dänzer 提交于
Otherwise the bit remains set in rdev->ih.rptr, so the wptr can never match that and we still have an infinite loop. This fix allows me to successfully recover from an IH ring buffer overflow. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 9月, 2014 1 次提交
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由 Alex Deucher 提交于
The packet seems to cause hangs on some 7xx asics. bug: https://bugs.freedesktop.org/show_bug.cgi?id=83616Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 27 8月, 2014 1 次提交
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由 Alex Deucher 提交于
This is a port of cedb655a to older asics. Fixes a possible divide by 0 if the harvest register is invalid. v2: drop some additional harvest munging. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 19 8月, 2014 2 次提交
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由 Christian König 提交于
Fixes lockups due to CP read GPUVM faults when running piglit on Cape Verde. v2 (chk): apply the fix to R600+ as well, on CIK only the GFX CP has a PFP, add more comments to R600 code, enable flushing again v3: (agd5f): only apply to 7xx+. r6xx does not have the packet. v4: (agd5f): split flush change into a separate patch, fix formatting Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Tested-by: NMichel Dänzer <michel.daenzer@amd.com>
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由 Michel Dänzer 提交于
It isn't necessary for command streams generated by the kernel (at least not while we aren't storing ring or indirect buffers in VRAM). Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 05 8月, 2014 4 次提交
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由 Mario Kleiner 提交于
Skip the "manual" pageflip completion checks via polling and guessing in the vblank handler radeon_crtc_handle_vblank() on asics which are known to reliably support hw pageflip completion irqs. Those pflip irqs are a more reliable and race-free method of handling pageflip completion detection, whereas the "classic" polling method has some small races in combination with dpm on, and with the reworked pageflip implementation since Linux 3.16. On old asics without pflip irqs, the classic method is used. On asics with known good pflip irqs, only pflip irqs are used by default, but a new module parameter "use_pflipirqs" allows to override this in case we encounter asics in the wild with unreliable or faulty pflip irqs. A module parameter of 0 allows to use the classic method only in such a case. A parameter of 1 allows to use both classic method and pflip irqs as additional band-aid to avoid some small races which could happen with the classic method alone. The setting 1 gives Linux 3.16 behaviour. Hw pflip irqs are available since R600. Tested on DCE-4, AMD Cedar - FirePro 2270. v2: agd5f: only enable pflip interrupts on DCE4+ as they are not reliable on older asics. Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michel Dänzer 提交于
And clean up the function comment a little. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michel Dänzer 提交于
v2: fix rebase onto drm-fixes Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michel Dänzer 提交于
Doesn't seem necessary, the GART table memory should be persistent. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 7月, 2014 1 次提交
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由 Christian König 提交于
We must mask out the overflow bit as well, otherwise the wptr will never match the rptr again and the interrupt handler will loop forever. Signed-off-by: NChristian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com>
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- 10 6月, 2014 2 次提交
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由 Alex Deucher 提交于
Query to find out how many compute units on a GPU. Useful for OpenCL usermode drivers. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Replace occurrences of "v & 0xffffffff" with lower_32_bits(v) when it's next to an upper_32_bits(v). Also remove unnecessary "upper_32_bits(v) & 0xffffffff" code snippets. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 6月, 2014 1 次提交
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由 Christian König 提交于
Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 06 5月, 2014 1 次提交
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由 Maarten Lankhorst 提交于
It would appear this bug has been copy/pasted many times without being noticed. Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
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- 01 5月, 2014 1 次提交
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由 Christian König 提交于
Testing the update pending bit directly after issuing an update is nonsense cause depending on the pixel clock the CRTC needs a bit of time to execute the flip even when we are in the VBLANK period. This is just a non invasive patch to solve the problem at hand, a more complete and cleaner solution should follow in the next merge window. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564 v2: fix source IDs for CRTC2-6 Signed-off-by: NChristian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
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- 07 3月, 2014 1 次提交
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由 Alex Deucher 提交于
Moving the pm resume up in the init order to fix dpm seems to have regressed somes cases with the old pm code. Move it back to late resume. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 2月, 2014 2 次提交
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由 Christian König 提交于
The reason for the false positives was fixed quite some time ago and since most engines can still execute NOPs while being locked up it leads to false negatives. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
In all cases where it really matters we are using the read functions anyway. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
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- 07 2月, 2014 1 次提交
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由 Alex Deucher 提交于
Otherwise decoding isn't really useable. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 30 1月, 2014 2 次提交
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由 Alex Deucher 提交于
If we are not able to properly initialize one of the gpu engines for buffer paging, we limit vram to the size of the cpu visible aperture. We generally either use the gfx or dma engine to do this. Clean up the size limiting code to only adjust the size based on what ring is selected for buffer paging rather than making assumptions about which engine is selected for paging. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com>
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由 Alex Deucher 提交于
The hw is buggy and it's not currently used, but it's currently still initialized by the driver. Skip the init. Skipping init also seems to improve stability with dpm on some r6xx asics. bug: https://bugs.freedesktop.org/show_bug.cgi?id=66963Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com>
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- 21 1月, 2014 1 次提交
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由 Alex Deucher 提交于
Needed to properly flush the read caches for fences. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 09 1月, 2014 1 次提交
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由 Alex Deucher 提交于
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. There's not much information still available on r6xx, so r6xx is based on guess-work. v2: put behind module parameter v3: add IGP check Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 25 12月, 2013 3 次提交
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由 Alex Deucher 提交于
Fill in asic family specific versions rather than using the generic version. This lets us handle asic specific differences more easily. In this case, we disable sw swapping of the rtpr writeback value on r6xx+ since the hw does it for us. Fixes bogus rptr readback on BE systems. v2: remove missed cpu_to_le32(), add comments Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
We need more control over the ordering of dpm init with respect to the rest of the asic. Specifically, the SMC has to be initialized before the rlc and cg/pg. The pm code currently initializes late in the driver, but we need it to happen much earlier so move pm handling into the asic specific callbacks. This makes dpm more reliable and makes clockgating work properly on CIK parts and should help on SI parts as well. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
We need to reorder the driver init sequence to better accomodate dpm which needs to be loaded earlier in the init sequence. Move fw init up so that it's available for dpm init. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 16 11月, 2013 1 次提交
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由 Christian König 提交于
To workaround bugs and/or certain limits it's sometimes useful to fall back to waiting on fences. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 02 11月, 2013 2 次提交
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由 Alex Deucher 提交于
Allows you to enable dither in the display hardware when the monitor supports lower a lower bpc than the current framebuffer format. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
The FMT blocks control how data is sent from the backend of the display pipe to to monitor. Proper set up of the FMT blocks are required for 30bpp formats. Additionally, dithering can be enabled on for better display with 18 and 24bpp displays. The exception is LVDS/eDP which atom takes care of in the SelectCRTC_Source table. For now just enable truncation until we test dithering more. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 10月, 2013 1 次提交
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由 Alex Deucher 提交于
Prevent driver load problems if the smc is missing. bug: https://bugzilla.kernel.org/show_bug.cgi?id=63011Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Tested-by: NMikko Rapeli <mikko.rapeli@iki.fi> Cc: stable@vger.kernel.org
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- 11 9月, 2013 2 次提交
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由 Alex Deucher 提交于
Certain r6xx boards use the same power state for both UVD and other things. Since we don't support UVD on r6xx boards at the moment, there was no callback installed for setting the UVD clocks, however, on systems that use the same power state, this leads to a NULL pointer dereference. Fill in a stubbed out implementation for now to avoid the crash. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66963Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: "3.11" <stable@vger.kernel.org>
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由 Alex Deucher 提交于
This adds spinlocks to protect access to other indirect register apertures. These indirect spaces are used pretty infrequently and we haven't had an reported problems, but better safe than sorry. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 8月, 2013 6 次提交
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由 Alex Deucher 提交于
The vram scratch buffer needs to be initialized before the mc is programmed otherwise we program 0 as the GPU address of the default GPU fault page. In most cases we put vram at zero anyway and reserve a page for the legacy vga buffer so in practice this shouldn't cause any problems, but better to make it correct. Was changed in: 6fab3febReported-by: NFrankR Huang <FrankR.Huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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由 Christian König 提交于
Similar to separating the UVD code, just put the DMA functions into separate files. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Our different hardware blocks are actually completely separated, so it doesn't make much sense any more to structure the code by pure chipset generations. Start restructuring the code by separating our the UVD block. v2: updated commit message v3: rebased and restructurized start/stop functions for kv dpm. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Now that we have callbacks for [rw]ptr handling we can remove the special handling for the DMA rings and use the callbacks instead. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
The hardware just doesn't support this correctly. Disable it before we accidentally write anywhere we shouldn't. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
When we PG (powergate) UVD, we need to re-initialize it before we can use it again. v2: rebase on UVD stop fixes Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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