- 17 11月, 2018 1 次提交
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由 Lubomir Rintel 提交于
A careless oversight. Sorry. Fixes: 0a897143b7c9 ("spi: pxa2xx: Add slave mode support") Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 14 11月, 2018 3 次提交
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由 Lubomir Rintel 提交于
There doesn't seem to be a way to empty TXFIFO on MMP2. The datasheet is super-secret and the method described in Armada 16x manual won't work: "The TXFIFO and RXFIFO are cleared to 0b0 when the SSPx port is reset or disabled (by writing a 0b0 to the <Synchronous Serial Port Enable> field in the SSP Control Register 0)." # devmem 0xd4037008 # read SSSR 0x0000F204 # devmem 0xd4037000 32 0x07 # SSE off in SSCR0 # devmem 0xd4037000 32 0x87 # SSE on # devmem 0xd4037008 0x0000F204 ^ TXFIFO level is still 2. Sigh. The OLPC 1.75 boot firmware leaves two bytes in the TXFIFO. Those are basically throwaway bytes used in response to the messages from the EC. The OLPC kernel copes with this by power-cycling the hardware. Perhaps the firmware should do this instead. Other than that, there's not much we can do other than complain loudly until the garbage gets drained and discard the actual data... For the OLPC EC this will work just fine and pushing more data to TXFIFO would break further transactions. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Acked-by: NPavel Machek <pavel@ucw.cz> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Lubomir Rintel 提交于
Strobe a GPIO line when the slave TX FIFO is filled. This is how the Embedded Controller on an OLPC XO-1.75 machine, that happens to be a SPI master, learns that it can initiate a transaction. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Tested-by: NPavel Machek <pavel@ucw.cz> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Lubomir Rintel 提交于
Tested on an OLPC XO-1.75 machine, where the Embedded Controller happens to be a SPI master. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Acked-by: NPavel Machek <pavel@ucw.cz> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 05 11月, 2018 1 次提交
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由 Jarkko Nikula 提交于
Intel LPSS private register restoring in spi-pxa2xx.c: pxa2xx_spi_resume() was added before there was no any other code restoring them. This was changed after following commits for previous and current LPSS platforms: c78b0830 ("ACPI / LPSS: custom power domain for LPSS") 41a3da2b ("mfd: intel-lpss: Save register context on suspend") However there is one caveat: There is no LPSS private register context save/restore for the Intel Lynxpoint in the Linux kernel code. I did some debugging on one Lynxpoint based device I have and on it the LPSS register context is not lost over suspend/resume cycle (s2idle). Which happens for instance on Intel Braswell. I'm speculating but I guess either firmware does it or the LPSS is kept always on Lynxpoint. Given that we haven't needed to implement Lynxpoint LPSS I2C or UART private register context save/restore over four years time I think we are safe to remove this LPSS private register restoring during resume here. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 11 10月, 2018 2 次提交
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由 Lubomir Rintel 提交于
The MMP2 platform, that uses device tree, has this controller. Let's add devicetree alongside platform & PCI. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Lubomir Rintel 提交于
That seems to be the correct type. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 04 10月, 2018 1 次提交
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由 Gustavo A. R. Silva 提交于
Rewrite switch code block to directly do the expected number of shifts in each case and have break statements. Addresses-Coverity-ID: 1056539 ("Missing break in switch") Suggested-by: NMark Brown <broonie@kernel.org> Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 18 9月, 2018 1 次提交
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由 Lubomir Rintel 提交于
It makes no sense to remove the device on shutdown. And it break things when the hardware crucial for shutdown (such as the embedded controller) is attached to the SPI bus. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 05 9月, 2018 1 次提交
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由 Geert Uytterhoeven 提交于
spi_controller_{suspend,resume}() already prints an error message on failure, so there is no need to repeat this in individual drivers. Note: spi_master_{suspend,resume}() is an alias for spi_controller_{suspend,resume}(). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NAlexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: NDaniel Mack <daniel@zonque.org> Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 28 6月, 2018 1 次提交
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由 Mika Westerberg 提交于
Intel Ice Lake SPI host controller follows the Intel Cannon Lake but the PCI IDs are different. Add the new PCI IDs to the driver supported devices list. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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- 04 5月, 2018 1 次提交
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由 Tobias Jordan 提交于
clk_prepare_enable() can fail, so its return value should be checked and acted upon. Found by Linux Driver Verification project (linuxtesting.org). Fixes: 3343b7a6 ("spi/pxa2xx: convert to the common clk framework") Signed-off-by: NTobias Jordan <Tobias.Jordan@elektrobit.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 18 4月, 2018 4 次提交
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由 kbuild test robot 提交于
Fixes: d5898e19 ("spi: pxa2xx: Use core message processing loop") Signed-off-by: NFengguang Wu <fengguang.wu@intel.com> Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
Convert the pump_transfers() transfer tasklet to transfer_one() hook the SPI core calls to process single transfer instead of handling message processing and chip select handling in the driver. This not only simplifies the driver but also brings transfer statistics from the core. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
We are going to rename and modify pump_transfers(). Prepare for it by removing the string "pump_transfers:" from error and warning prints. While at it make these user-visible strings single line in sources as it helps source grepping from error reports. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
Current DMA engine implementation of pxa2xx_spi_dma_prepare() don't use the dma_burst argument. Remove it since it became unused after commit 6356437e ("spi: spi-pxa2xx: remove legacy PXA DMA bits"). Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 07 3月, 2018 1 次提交
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由 Jarkko Nikula 提交于
Don't leave runtime PM enabled in case devm_spi_register_controller() returns with an error. Otherwise runtime PM will complain when driver is reloaded: [ 693.855811] pxa2xx-spi pxa2xx-spi.13: Unbalanced pm_runtime_enable! Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 12 2月, 2018 2 次提交
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由 Jarkko Nikula 提交于
Convert to generalized SPI controller API introduced by the commit 8caab75f ("spi: Generalize SPI "master" to "controller""). Inside driver variable name "master" is still used to indicate the driver is master only. While at it, change "unsigned cs" to "unsigned int cs" in pxa2xx_spi_fw_translate_cs() to suppress checkpatch warning. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
Move SSP idle waiting before CS deassert from error and end of message handling function giveback() to cs_deassert(). This ensures idle waiting is done also if there is CS change between transfers. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 23 12月, 2017 1 次提交
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由 Mark Brown 提交于
gpiod_free() is an internal function for gpiolib, gpiod_put() is the correct external function. Reported-by: NStephen Rothwell <sfr@canb.auug.org.au> Suggested-by: NRasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 21 12月, 2017 1 次提交
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由 Rasmus Villemoes 提交于
gpio_free(gpio) simply does gpiod_free(gpio_to_desc(gpio)), so it's simpler and cleaner to use gpiod_free directly. Signed-off-by: NRasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 04 8月, 2017 1 次提交
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由 Jan Kiszka 提交于
We still need to request/free GPIOs passed via the legacy path of pxa2xx_spi_chip::gpio_cs, but we can use the gpiod API otherwise. Consistently use the descriptor API instead of the legacy one. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 28 7月, 2017 2 次提交
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由 Andy Shevchenko 提交于
GPIO descriptors, when being requested, may configure pin at the same time. In case of SPI chip select we shouldn't do any assumptions of the state of pin since we don't know yet what chip is connected there and if it uses high or low active state. So, leave the state of pin as is until transfer will start. Fixes: 99f499cd ("spi: pxa2xx: Add support for GPIO descriptor chip selects") Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: NMika Westeberg <mika.westerberg@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Andy Shevchenko 提交于
There is a valid case to call setup() following by setup_cs() several times for the same chip. With the commit 676a4e3b ("spi: pxa2xx: Only claim CS GPIOs when the slave device is created") it is not possible anymore due to GPIO line being requested already during the first call to setup_cs(). For now, revert the commit to make things work again. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 17 7月, 2017 1 次提交
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由 Jan Kiszka 提交于
Avoid hogging chip select GPIOs just because they are listed for the master. They might be mulitplexed and, if no slave device is attached, used for different purposes. Moreover, this strategy avoids having to allocate a cs_gpiods structure. Tested on the IOT2000 where the second SPI bus is connected to an Arduino-compatible connector and multiplexed between SPI, GPIO and PWM usage. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 07 6月, 2017 1 次提交
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由 Jarkko Nikula 提交于
Intel Cannonlake LPSS SPI has up to four chip selects per port like in Broxton and is clocked like Sunrisepoint and Kaby Lake. Add a new type LPSS_CNL_SSP and configuration that enable runtime chip select detection and use the same FIFO thresholds than in Sunrisepoint. Patch adds support for both Cannonlake SoC and PCH. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 24 1月, 2017 1 次提交
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由 Jan Kiszka 提交于
When using the a device with edge-triggered interrupts, such as MSIs, the interrupt handler has to ensure that there is a point in time during its execution where all interrupts sources are silent so that a new event can trigger a new interrupt again. This is achieved here by disabling all interrupt sources for a moment before processing them according to the status register. If a new interrupt should have arrived after we read the status, it will now re-trigger the interrupt, even in edge mode. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 19 1月, 2017 1 次提交
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由 David E. Box 提交于
Gemini Lake reuses the same LPSS SPI configuration as Broxton Signed-off-by: NDavid E. Box <david.e.box@linux.intel.com> Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 18 1月, 2017 1 次提交
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由 Jan Kiszka 提交于
As suggested by Andy Shevchenko: Decouple this corner cause from the general handling logic in ssp_int. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 05 1月, 2017 1 次提交
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由 Andy Shevchenko 提交于
The commit 7c7289a4 ("spi: pxa2xx: Default thresholds to PXA configuration") while splitting up CE4100 code obviously missed a break condition in one chunk. Add it here. Looks like we have no active user of CE4100, though better to fix this later than never. Fixes: commit 7c7289a4 ("spi: pxa2xx: Default thresholds to PXA configuration") Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 30 9月, 2016 1 次提交
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由 Mika Westerberg 提交于
Kbuild test robot reports: drivers/spi/spi-pxa2xx.c: In function ‘setup_cs’: drivers/spi/spi-pxa2xx.c:1190:20: error: implicit declaration of function ‘desc_to_gpio’ ... Reason for this is the fact that those functions are declared in linux/gpio/consumer.h which is not included in the driver. Fix this by including it. Reported-by: Nkbuild test robot <fengguang.wu@intel.com> Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 27 9月, 2016 1 次提交
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由 Mika Westerberg 提交于
The driver uses custom chip_info coming from platform data for chip selects implemented as GPIOs. If the system lacks board files setting up the platform data, it is not possible to use GPIOs as chip selects. This adds support for GPIO descriptors so that regardless of the underlying firmware interface (DT, ACPI or platform data) the driver can request GPIOs used as chip selects and configure them accordingly. The custom chip_info GPIO support is still left there to make sure the existing systems keep working as expected. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 13 9月, 2016 4 次提交
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由 Andy Shevchenko 提交于
Most of the devices in the supported list have PXA configuration of FIFO. In particularly Intel Medfield and Merrifield have bigger FIFO, than it's defined for CE4100. Split CE4100 in the similar way how it was done for Intel Quark, i.e. prefix definitions by CE4100 and append necessary pieces of code to switch case conditions. We are on safe side since those bits are ignored on all LPSS IPs. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
Transfer state machine in this driver does not need to set/unset pointer to chip data between queueing and finalizing message as it is not actually used as a state info itself but just pointer passing. Since this per SPI device specific chip data is already carried in ctldata use that and remove pointer to chip data from driver data. While at it, group initialized variables before uninitialized variables in pump_transfers(). Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
There is no need to carry pointer to current SPI message in driver data because cur_msg in struct spi_master holds it already when driver is using the message queueing infrastructure from the SPI core. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
All of these variables are unconditionally set before their use. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 07 7月, 2016 1 次提交
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由 Andy Shevchenko 提交于
It seems the commit e5262d05 ("spi: spi-pxa2xx: SPI support for Intel Quark X1000") misses one place to be adapted for Intel Quark, i.e. in reset_sccr1(). Clear all RFT bits when call reset_sccr1() on Intel Quark. Fixes: e5262d05 ("spi: spi-pxa2xx: SPI support for Intel Quark X1000") Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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- 04 7月, 2016 1 次提交
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由 Mika Westerberg 提交于
Kaby Lake PCH-H has the same SPI host controller as Skylake. Add these new PCI IDs to the list of supported devices. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 22 6月, 2016 2 次提交
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由 Jarkko Nikula 提交于
SPI core provides DMA mapping with scatterlists. Start using it instead of own implementation in spi-pxa2xx. Major difference in addition to bunch of removed boilerplate code is that SPI core does mapping/unmapping for all transfers in a message before and after the message sending where spi-pxa2xx did mapping/unmapping for each transfers separately. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
We will find more use for struct spi_master pointer in pump_transfers() and code will be more readable if we access it using local pointer than through the drv_data->master. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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