- 05 11月, 2018 1 次提交
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由 Chuanhua Han 提交于
Some SoC share one irq number between DSPI controllers. For example, on the LX2160 board, DSPI0 and DSPI1 share one irq number. In this case, only one DSPI controller can register successfully, and others will fail. Signed-off-by: NChuanhua Han <chuanhua.han@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 29 8月, 2018 1 次提交
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由 Angelo Dureghello 提交于
This patch fixes the dspi_eoq_write function used by the ColdFire mcf5441x family. The 16 bit cmd part must be re-set at each data transfer. Also, now that fifo_size variables are used for eoq_read/write, a proper fifo size must be set (16 slots for the ColdFire dspi module version). Signed-off-by: NAngelo Dureghello <angelo@sysam.it> Acked-by: NEsben Haabendal <esben@haabendal.dk> Signed-off-by: NMark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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- 24 7月, 2018 1 次提交
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由 Fabio Estevam 提交于
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 17 7月, 2018 1 次提交
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由 Andrey Smirnov 提交于
Upper layer users of SPI device drivers may rely on 'actual_length', so it is important that information is correctly reported. One such example is spi_mem_exec_op() function that will fail if 'actual_length' of the data transferred is not what was requested. Add necessary code to populate 'actual_length. Cc: Mark Brown <broonie@kernel.org> Cc: Sanchayan Maity <maitysanchayan@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: cphealy@gmail.com Cc: linux-spi@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 02 7月, 2018 1 次提交
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由 Krzysztof Kozlowski 提交于
Registers of DSPI should not be accessed before enabling its clock. On Toradex Colibri VF50 on Iris carrier board this could be seen during bootup as imprecise abort: Unhandled fault: imprecise external abort (0x1c06) at 0x00000000 Internal error: : 1c06 [#1] ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper Not tainted 4.14.39-dirty #97 Hardware name: Freescale Vybrid VF5xx/VF6xx (Device Tree) Backtrace: [<804166a8>] (regmap_write) from [<80466b5c>] (dspi_probe+0x1f0/0x8dc) [<8046696c>] (dspi_probe) from [<8040107c>] (platform_drv_probe+0x54/0xb8) [<80401028>] (platform_drv_probe) from [<803ff53c>] (driver_probe_device+0x280/0x2f8) [<803ff2bc>] (driver_probe_device) from [<803ff674>] (__driver_attach+0xc0/0xc4) [<803ff5b4>] (__driver_attach) from [<803fd818>] (bus_for_each_dev+0x70/0xa4) [<803fd7a8>] (bus_for_each_dev) from [<803fee74>] (driver_attach+0x24/0x28) [<803fee50>] (driver_attach) from [<803fe980>] (bus_add_driver+0x1a0/0x218) [<803fe7e0>] (bus_add_driver) from [<803fffe8>] (driver_register+0x80/0x100) [<803fff68>] (driver_register) from [<80400fdc>] (__platform_driver_register+0x48/0x50) [<80400f94>] (__platform_driver_register) from [<8091cf7c>] (fsl_dspi_driver_init+0x1c/0x20) [<8091cf60>] (fsl_dspi_driver_init) from [<8010195c>] (do_one_initcall+0x4c/0x174) [<80101910>] (do_one_initcall) from [<80900e8c>] (kernel_init_freeable+0x144/0x1d8) [<80900d48>] (kernel_init_freeable) from [<805ff6a8>] (kernel_init+0x10/0x114) [<805ff698>] (kernel_init) from [<80107be8>] (ret_from_fork+0x14/0x2c) Cc: <stable@vger.kernel.org> Fixes: 5ee67b58 ("spi: dspi: clear SPI_SR before enable interrupt") Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 21 6月, 2018 1 次提交
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由 Gustavo A. R. Silva 提交于
It seems that the proper structure field to use in this particular case is *regmap_pushr* instead of regmap. Addresses-Coverity-ID: 1470126 ("Copy-paste error") Fixes: 58ba07ec ("spi: spi-fsl-dspi: Add support for XSPI mode registers") Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com> Acked-by: NEsben Haabendal <eha@deif.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 20 6月, 2018 12 次提交
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由 Esben Haabendal 提交于
Set the XSPI bit for devices configured for XSPI mode (currently LS1021A), and thereby switch to extended SPI mode, allowing for SPI transfers using from 4 to 32 bits per word instead of 4 to 16 bits per word. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
This implements handling of split CMD and TX FIFO queues for XSPI when running in TCFQ mode. It should be simple to add it to EOQ mode also. Currently, EOQ mode is only used with coldfire. So if coldfire DSPI supports XSPI, XSPI FIFO handling should be added to EOQ mode also. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
This prepares for adding support for extended SPI mode (XSPI), by extending the regmap with the extra SREX and CTAREx registers. An additional register map is made for allowing 16 bit access to CMD and TX FIFO of the PUSHR register separately, which is also needed for XSPI mode support. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
Mark volatile registers to avoid caching bugs. Note: SPI_MCR is marked volatile because of CLR_TXF and CLR_RXF bits. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
The MCR register is not changed, so initialize it in dspi_init(). The exception is the CLR_TXF and CLR_RXF bits, which should be written to before each transfer to make sure we start with empty FIFOs. With MCR register now configured as volatile, the regmap_update_bits will do a real read-modify-write cycle. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
This extends the driver with support for all SPI framesizes from 4 to 16 bits, and adds support for per transfer specific bits_per_word, while at the same time reducing code size and complexity. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
Simplify driver by avoiding counter wrapping by clearing transfer counter on first SPI transfer per interrupt instead of tracking what it was before. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
As of 92dc20d8, transfer->cs_change has been supported for non-last transfers, but not for last transfer. This change brings handling of cs_change in line with the specification in spi.h, implementing handling of transfer->cs_change for all transfers. The value for CMD FIFO is precalculated with transfer->cs_change field taken into account, allowing for CS de-activate between transfers and keeping CS activated after last transfer. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
Checking directly against pointer value should be at least as fast as doing bitmasking and compare, so let's keep it simple. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Esben Haabendal 提交于
The if statement just above this if/else statement triggers on the same condition, and then invalidates it. Signed-off-by: NEsben Haabendal <eha@deif.com> Acked-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 03 1月, 2018 1 次提交
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由 Julia Lawall 提交于
This driver creates a number of const structures that it stores in the data field of an of_device_id array. The data field of an of_device_id structure has type const void *, so there is no need for a const-discarding cast when putting const values into such a structure. Done using Coccinelle. Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 16 11月, 2017 1 次提交
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由 Kurt Kanzenbach 提交于
The driver as well as the controller support the SPI lsb first mode. However, it's not possible to configure it e.g. when using spidev. Adding this flag to mode_bits resolves the issue and lsb first mode can be used. Signed-off-by: NKurt Kanzenbach <kurt@linutronix.de> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 03 11月, 2017 1 次提交
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由 Angelo Dureghello 提交于
Signed-off-by: NAngelo Dureghello <angelo@sysam.it> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 22 5月, 2017 1 次提交
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由 Nikita Yushchenko 提交于
Propagate error return from dspi_request_dma() into probe routine's return. Signed-off-by: NNikita Yushchenko <nikita.yoush@cogentembedded.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 20 2月, 2017 1 次提交
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由 Christophe JAILLET 提交于
According to error handling in this function, it is likely that going to 'out_master_put' was expected here. Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 23 11月, 2016 3 次提交
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由 Sanchayan Maity 提交于
Current DMA implementation was not handling the continuous selection format viz. SPI chip select would be deasserted even between sequential serial transfers. Use existing dspi_data_to_pushr function to restructure the transmit code path and set or reset the CONT bit on same lines as code path in EOQ mode does. This correctly implements continuous selection format while also correcting and cleaning up the transmit code path. Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Sanchayan Maity 提交于
Currently dmaengine_prep_slave_single was being called with length set to the complete DMA buffer size. This resulted in unwanted bytes being transferred to the SPI register leading to clock and MOSI lines having unwanted data even after chip select got deasserted and the required bytes having been transferred. While at it also clean up the use of curr_xfer_len which is central to the DMA setup, from bytes to DMA transfers for every use. Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Sanchayan Maity 提交于
Buffers allocated with a call to dma_alloc_coherent should be freed with dma_free_coherent instead of the currently used devm_kfree. Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 18 11月, 2016 1 次提交
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由 Sanchayan Maity 提交于
Current DMA implementation had a bug where the DMA transfer would exit the loop in dspi_transfer_one_message after the completion of a single transfer. This results in a multi message transfer submitted with SPI_IOC_MESSAGE to terminate incorrectly without an error. Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 11 11月, 2016 1 次提交
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由 Sanchayan Maity 提交于
Add DMA support for Vybrid. Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 30 10月, 2016 1 次提交
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由 Yuan Yao 提交于
Once dspi is used in uboot, the SPI_SR have been set by some value. At this time, if kernel enable the interrupt before clear the status flag, that will trigger the wrong interrupt. Signed-off-by: NYuan Yao <yao.yuan@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 23 8月, 2016 2 次提交
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由 Wei Yongjun 提交于
The call sequence spi_alloc_master/spi_register_master/spi_unregister_master is complete; it reduces the device reference count to zero, which and results in device memory being freed. The subsequent call to spi_master_put is unnecessary and results in an access to free memory. Drop it. Fixes: 9298bc72 ("spi: spi-fsl-dspi: Remove spi-bitbang") Signed-off-by: NWei Yongjun <weiyj.lk@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Fabio Estevam 提交于
clk_prepare_enable() may fail, so we should better check its return value and propagate it in the case of failure. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 16 8月, 2016 2 次提交
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由 LABBE Corentin 提交于
of_match_device could return NULL, and so cause a NULL pointer dereference later. For fixing this problem, we use of_device_get_match_data(), this will simplify the code a little by using a standard function for getting the match data. Reported-by: coverity (CID 1324129) Signed-off-by: NLABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 LABBE Corentin 提交于
of_id->data is const, so instead of casting the pointer to drop its const status, this patch constify the devtype_data pointer. Signed-off-by: NLABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 06 4月, 2016 1 次提交
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由 Andrey Vostrikov 提交于
There are use cases when chip select should be triggered between transfers in single SPI message. Current implementation does this only on last transfer in message ignoring cs_change value provided in current transfer. Signed-off-by: NAndrey Vostrikov <andrey.vostrikov@cogentembedded.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 23 3月, 2016 1 次提交
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由 Bhuvanchandra DV 提交于
Calculate and update max speed from bus clock for SoCs using DSPI IP. The bus clock factor's are taken from the data sheets of respective SoCs. Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 13 12月, 2015 1 次提交
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由 Bhuvanchandra DV 提交于
DSPI instances in Vybrid have a different amount of chip selects and CTARs (Clock and transfer Attributes Register). In case of DSPI1 we only have 2 CTAR registers and 4 CS. In present driver implementation CTAR offset is derived from CS instance which will lead to out of bound access if chip select instance is greater than CTAR register instance, hence use single CTAR0 register for all CS instances. Since we write the CTAR register anyway before each access, there is no value in using the additional CTAR registers. Also one should not program a value in CTAS for a CTAR register that is not present, hence configure CTAS to use CTAR0. Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 18 9月, 2015 1 次提交
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由 Jarkko Nikula 提交于
SPI core makes sure that transfer speed is always set so code here writes the same register with the same value twice. Code has been doing this from the beginning. This looks to me some sort of copy paste error so I'm removing the second write. If this is not the case we can bring it back with a comment. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 13 6月, 2015 1 次提交
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由 Mirza Krak 提交于
Add support for "sleep" state of pinctrl. Signed-off-by: NMirza Krak <mirza.krak@hostmobility.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 10 6月, 2015 2 次提交
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由 Haikun Wang 提交于
In current driver, we increase actual_length in the following way: message->actual_length += dspi_xxx_transfer() It has two defects. First, transmitting maybe in process when the function call finished and we don't know the transmitting result in this moment. Secondly, the last sentence in function before returning is accessing the SPI register and trigger the data transmitting. If we enable interrupt, interrupt may be generated before function return and we also have the same sentence "message->actual_length += dspi_xxx_transfer()" in the IRQ handler. And usually dspi_xxx_transfer will trigger a new IRQ. The original dspi_xxx_transfer call may return when no new IRQ generate. This may mess the variable spi_message->actual_length. Now we increase the variable in the IRQ handler and only when we get the TCF or EOQ interrupt And we get the transmitted data length from the SPI transfer counter instead of the function return value. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Haikun Wang 提交于
DSPI module has two optional interrupts when complete data transfer. One is EOQ interrupt, the other one is TCF interrupt. EOQ indicates a queue of data frame has been transmitted. TCF indicates a frame has been transmitted. This patch enable support TCF mode. Driver binds a correct interrupt mode to every compatible string. User should use the correct compatible string in the dts node. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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