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ff4b42c7
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ff4b42c7
编写于
11年前
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nouveau/pwr: initial implementation
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
682b1fc7
变更
30
展开全部
隐藏空白更改
内联
并排
Showing
30 changed file
with
7091 addition
and
0 deletion
+7091
-0
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/Makefile
+6
-0
drivers/gpu/drm/nouveau/core/engine/device/base.c
drivers/gpu/drm/nouveau/core/engine/device/base.c
+1
-0
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+5
-0
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+9
-0
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+6
-0
drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
+80
-0
drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
+1
-0
drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
+1
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
+247
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
+151
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc
+84
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
+452
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
+199
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
+219
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
+63
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
+1165
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
+63
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
+1229
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
+63
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
+1229
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
+63
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
+1229
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
+27
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc
+57
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc
+64
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
+121
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
+62
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
+71
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
+62
-0
drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
+62
-0
未找到文件。
drivers/gpu/drm/nouveau/Makefile
浏览文件 @
ff4b42c7
...
...
@@ -129,6 +129,12 @@ nouveau-y += core/subdev/mc/nvc3.o
nouveau-y
+=
core/subdev/mxm/base.o
nouveau-y
+=
core/subdev/mxm/mxms.o
nouveau-y
+=
core/subdev/mxm/nv50.o
nouveau-y
+=
core/subdev/pwr/base.o
nouveau-y
+=
core/subdev/pwr/memx.o
nouveau-y
+=
core/subdev/pwr/nva3.o
nouveau-y
+=
core/subdev/pwr/nvc0.o
nouveau-y
+=
core/subdev/pwr/nvd0.o
nouveau-y
+=
core/subdev/pwr/nv108.o
nouveau-y
+=
core/subdev/therm/base.o
nouveau-y
+=
core/subdev/therm/fan.o
nouveau-y
+=
core/subdev/therm/fannil.o
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/engine/device/base.c
浏览文件 @
ff4b42c7
...
...
@@ -75,6 +75,7 @@ static const u64 disable_map[] = {
[
NVDEV_SUBDEV_BAR
]
=
NV_DEVICE_DISABLE_CORE
,
[
NVDEV_SUBDEV_VOLT
]
=
NV_DEVICE_DISABLE_CORE
,
[
NVDEV_SUBDEV_THERM
]
=
NV_DEVICE_DISABLE_CORE
,
[
NVDEV_SUBDEV_PWR
]
=
NV_DEVICE_DISABLE_CORE
,
[
NVDEV_ENGINE_DMAOBJ
]
=
NV_DEVICE_DISABLE_CORE
,
[
NVDEV_ENGINE_FIFO
]
=
NV_DEVICE_DISABLE_FIFO
,
[
NVDEV_ENGINE_SW
]
=
NV_DEVICE_DISABLE_FIFO
,
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
浏览文件 @
ff4b42c7
...
...
@@ -36,6 +36,7 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/pwr.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
...
...
@@ -327,6 +328,7 @@ nv50_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nv50_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nv50_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nva3_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nv50_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nv84_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nv50_software_oclass
;
...
...
@@ -354,6 +356,7 @@ nv50_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nv50_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nv50_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nva3_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nv50_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nv84_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nv50_software_oclass
;
...
...
@@ -380,6 +383,7 @@ nv50_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nv50_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nv50_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nva3_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nv50_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nv84_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nv50_software_oclass
;
...
...
@@ -406,6 +410,7 @@ nv50_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nv50_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nv50_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nva3_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nv50_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nv84_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nv50_software_oclass
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
浏览文件 @
ff4b42c7
...
...
@@ -38,6 +38,7 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/pwr.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
...
...
@@ -72,6 +73,7 @@ nvc0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvc0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvc0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nvc0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -101,6 +103,7 @@ nvc0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvc0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvc0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nvc0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -130,6 +133,7 @@ nvc0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvc0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvc0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nvc0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -158,6 +162,7 @@ nvc0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvc0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvc0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nvc0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -187,6 +192,7 @@ nvc0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvc0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvc0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nvc0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -216,6 +222,7 @@ nvc0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvc0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvc0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nvc0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -244,6 +251,7 @@ nvc0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvc0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvc0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nvc0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -273,6 +281,7 @@ nvc0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvd0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvd0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nvc0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
浏览文件 @
ff4b42c7
...
...
@@ -38,6 +38,7 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/pwr.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
...
...
@@ -72,6 +73,7 @@ nve0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvd0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvd0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nve0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -102,6 +104,7 @@ nve0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvd0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvd0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nve0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -132,6 +135,7 @@ nve0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvd0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvd0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nve0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -162,6 +166,7 @@ nve0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nvd0_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvd0_dmaeng_oclass
;
device
->
oclass
[
NVDEV_ENGINE_FIFO
]
=
nve0_fifo_oclass
;
device
->
oclass
[
NVDEV_ENGINE_SW
]
=
nvc0_software_oclass
;
...
...
@@ -194,6 +199,7 @@ nve0_identify(struct nouveau_device *device)
device
->
oclass
[
NVDEV_SUBDEV_INSTMEM
]
=
&
nv50_instmem_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_VM
]
=
&
nvc0_vmmgr_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_BAR
]
=
&
nvc0_bar_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_PWR
]
=
&
nv108_pwr_oclass
;
device
->
oclass
[
NVDEV_ENGINE_DMAOBJ
]
=
&
nvd0_dmaeng_oclass
;
#if 0
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
0 → 100644
浏览文件 @
ff4b42c7
#ifndef __NOUVEAU_PWR_H__
#define __NOUVEAU_PWR_H__
#include <core/subdev.h>
#include <core/device.h>
struct
nouveau_pwr
{
struct
nouveau_subdev
base
;
struct
{
u32
limit
;
u32
*
data
;
u32
size
;
}
code
;
struct
{
u32
limit
;
u32
*
data
;
u32
size
;
}
data
;
struct
{
u32
base
;
u32
size
;
}
send
;
struct
{
u32
base
;
u32
size
;
struct
work_struct
work
;
wait_queue_head_t
wait
;
u32
process
;
u32
message
;
u32
data
[
2
];
}
recv
;
int
(
*
message
)(
struct
nouveau_pwr
*
,
u32
[
2
],
u32
,
u32
,
u32
,
u32
);
};
static
inline
struct
nouveau_pwr
*
nouveau_pwr
(
void
*
obj
)
{
return
(
void
*
)
nv_device
(
obj
)
->
subdev
[
NVDEV_SUBDEV_PWR
];
}
#define nouveau_pwr_create(p, e, o, d) \
nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_pwr_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_pwr_init(p) ({ \
struct nouveau_pwr *ppwr = (p); \
_nouveau_pwr_init(nv_object(ppwr)); \
})
#define nouveau_pwr_fini(p,s) ({ \
struct nouveau_pwr *ppwr = (p); \
_nouveau_pwr_fini(nv_object(ppwr), (s)); \
})
int
nouveau_pwr_create_
(
struct
nouveau_object
*
,
struct
nouveau_object
*
,
struct
nouveau_oclass
*
,
int
,
void
**
);
#define _nouveau_pwr_dtor _nouveau_subdev_dtor
int
_nouveau_pwr_init
(
struct
nouveau_object
*
);
int
_nouveau_pwr_fini
(
struct
nouveau_object
*
,
bool
);
extern
struct
nouveau_oclass
nva3_pwr_oclass
;
extern
struct
nouveau_oclass
nvc0_pwr_oclass
;
extern
struct
nouveau_oclass
nvd0_pwr_oclass
;
extern
struct
nouveau_oclass
nv108_pwr_oclass
;
/* interface to MEMX process running on PPWR */
struct
nouveau_memx
;
int
nouveau_memx_init
(
struct
nouveau_pwr
*
,
struct
nouveau_memx
**
);
int
nouveau_memx_fini
(
struct
nouveau_memx
**
,
bool
exec
);
void
nouveau_memx_wr32
(
struct
nouveau_memx
*
,
u32
addr
,
u32
data
);
void
nouveau_memx_wait
(
struct
nouveau_memx
*
,
u32
addr
,
u32
mask
,
u32
data
,
u32
nsec
);
void
nouveau_memx_nsec
(
struct
nouveau_memx
*
,
u32
nsec
);
#endif
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
浏览文件 @
ff4b42c7
...
...
@@ -32,6 +32,7 @@ nv98_mc_intr[] = {
{
0x00004000
,
NVDEV_ENGINE_CRYPT
},
/* NV84:NVA3 */
{
0x00008000
,
NVDEV_ENGINE_BSP
},
{
0x00020000
,
NVDEV_ENGINE_VP
},
{
0x00040000
,
NVDEV_SUBDEV_PWR
},
/* NVA3:NVC0 */
{
0x00080000
,
NVDEV_SUBDEV_THERM
},
/* NVA3:NVC0 */
{
0x00100000
,
NVDEV_SUBDEV_TIMER
},
{
0x00200000
,
NVDEV_SUBDEV_GPIO
},
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
浏览文件 @
ff4b42c7
...
...
@@ -37,6 +37,7 @@ nvc0_mc_intr[] = {
{
0x00020000
,
NVDEV_ENGINE_VP
},
{
0x00100000
,
NVDEV_SUBDEV_TIMER
},
{
0x00200000
,
NVDEV_SUBDEV_GPIO
},
{
0x01000000
,
NVDEV_SUBDEV_PWR
},
{
0x02000000
,
NVDEV_SUBDEV_LTCG
},
{
0x04000000
,
NVDEV_ENGINE_DISP
},
{
0x10000000
,
NVDEV_SUBDEV_BUS
},
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include <subdev/timer.h>
static
int
nouveau_pwr_send
(
struct
nouveau_pwr
*
ppwr
,
u32
reply
[
2
],
u32
process
,
u32
message
,
u32
data0
,
u32
data1
)
{
struct
nouveau_subdev
*
subdev
=
nv_subdev
(
ppwr
);
u32
addr
;
/* we currently only support a single process at a time waiting
* on a synchronous reply, take the PPWR mutex and tell the
* receive handler what we're waiting for
*/
if
(
reply
)
{
mutex_lock
(
&
subdev
->
mutex
);
ppwr
->
recv
.
message
=
message
;
ppwr
->
recv
.
process
=
process
;
}
/* wait for a free slot in the fifo */
addr
=
nv_rd32
(
ppwr
,
0x10a4a0
);
if
(
!
nv_wait_ne
(
ppwr
,
0x10a4b0
,
0xffffffff
,
addr
^
8
))
return
-
EBUSY
;
/* acquire data segment access */
do
{
nv_wr32
(
ppwr
,
0x10a580
,
0x00000001
);
}
while
(
nv_rd32
(
ppwr
,
0x10a580
)
!=
0x00000001
);
/* write the packet */
nv_wr32
(
ppwr
,
0x10a1c0
,
0x01000000
|
(((
addr
&
0x07
)
<<
4
)
+
ppwr
->
send
.
base
));
nv_wr32
(
ppwr
,
0x10a1c4
,
process
);
nv_wr32
(
ppwr
,
0x10a1c4
,
message
);
nv_wr32
(
ppwr
,
0x10a1c4
,
data0
);
nv_wr32
(
ppwr
,
0x10a1c4
,
data1
);
nv_wr32
(
ppwr
,
0x10a4a0
,
(
addr
+
1
)
&
0x0f
);
/* release data segment access */
nv_wr32
(
ppwr
,
0x10a580
,
0x00000000
);
/* wait for reply, if requested */
if
(
reply
)
{
wait_event
(
ppwr
->
recv
.
wait
,
(
ppwr
->
recv
.
process
==
0
));
reply
[
0
]
=
ppwr
->
recv
.
data
[
0
];
reply
[
1
]
=
ppwr
->
recv
.
data
[
1
];
mutex_unlock
(
&
subdev
->
mutex
);
}
return
0
;
}
static
void
nouveau_pwr_recv
(
struct
work_struct
*
work
)
{
struct
nouveau_pwr
*
ppwr
=
container_of
(
work
,
struct
nouveau_pwr
,
recv
.
work
);
u32
process
,
message
,
data0
,
data1
;
/* nothing to do if GET == PUT */
u32
addr
=
nv_rd32
(
ppwr
,
0x10a4cc
);
if
(
addr
==
nv_rd32
(
ppwr
,
0x10a4c8
))
return
;
/* acquire data segment access */
do
{
nv_wr32
(
ppwr
,
0x10a580
,
0x00000002
);
}
while
(
nv_rd32
(
ppwr
,
0x10a580
)
!=
0x00000002
);
/* read the packet */
nv_wr32
(
ppwr
,
0x10a1c0
,
0x02000000
|
(((
addr
&
0x07
)
<<
4
)
+
ppwr
->
recv
.
base
));
process
=
nv_rd32
(
ppwr
,
0x10a1c4
);
message
=
nv_rd32
(
ppwr
,
0x10a1c4
);
data0
=
nv_rd32
(
ppwr
,
0x10a1c4
);
data1
=
nv_rd32
(
ppwr
,
0x10a1c4
);
nv_wr32
(
ppwr
,
0x10a4cc
,
(
addr
+
1
)
&
0x0f
);
/* release data segment access */
nv_wr32
(
ppwr
,
0x10a580
,
0x00000000
);
/* wake process if it's waiting on a synchronous reply */
if
(
ppwr
->
recv
.
process
)
{
if
(
process
==
ppwr
->
recv
.
process
&&
message
==
ppwr
->
recv
.
message
)
{
ppwr
->
recv
.
data
[
0
]
=
data0
;
ppwr
->
recv
.
data
[
1
]
=
data1
;
ppwr
->
recv
.
process
=
0
;
wake_up
(
&
ppwr
->
recv
.
wait
);
return
;
}
}
/* right now there's no other expected responses from the engine,
* so assume that any unexpected message is an error.
*/
nv_warn
(
ppwr
,
"%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x
\n
"
,
(
char
)((
process
&
0x000000ff
)
>>
0
),
(
char
)((
process
&
0x0000ff00
)
>>
8
),
(
char
)((
process
&
0x00ff0000
)
>>
16
),
(
char
)((
process
&
0xff000000
)
>>
24
),
process
,
message
,
data0
,
data1
);
}
static
void
nouveau_pwr_intr
(
struct
nouveau_subdev
*
subdev
)
{
struct
nouveau_pwr
*
ppwr
=
(
void
*
)
subdev
;
u32
disp
=
nv_rd32
(
ppwr
,
0x10a01c
);
u32
intr
=
nv_rd32
(
ppwr
,
0x10a008
)
&
disp
&
~
(
disp
>>
16
);
if
(
intr
&
0x00000020
)
{
u32
stat
=
nv_rd32
(
ppwr
,
0x10a16c
);
if
(
stat
&
0x80000000
)
{
nv_error
(
ppwr
,
"UAS fault at 0x%06x addr 0x%08x
\n
"
,
stat
&
0x00ffffff
,
nv_rd32
(
ppwr
,
0x10a168
));
nv_wr32
(
ppwr
,
0x10a16c
,
0x00000000
);
intr
&=
~
0x00000020
;
}
}
if
(
intr
&
0x00000040
)
{
schedule_work
(
&
ppwr
->
recv
.
work
);
nv_wr32
(
ppwr
,
0x10a004
,
0x00000040
);
intr
&=
~
0x00000040
;
}
if
(
intr
&
0x00000080
)
{
nv_info
(
ppwr
,
"wr32 0x%06x 0x%08x
\n
"
,
nv_rd32
(
ppwr
,
0x10a7a0
),
nv_rd32
(
ppwr
,
0x10a7a4
));
nv_wr32
(
ppwr
,
0x10a004
,
0x00000080
);
intr
&=
~
0x00000080
;
}
if
(
intr
)
{
nv_error
(
ppwr
,
"intr 0x%08x
\n
"
,
intr
);
nv_wr32
(
ppwr
,
0x10a004
,
intr
);
}
}
int
_nouveau_pwr_fini
(
struct
nouveau_object
*
object
,
bool
suspend
)
{
struct
nouveau_pwr
*
ppwr
=
(
void
*
)
object
;
nv_wr32
(
ppwr
,
0x10a014
,
0x00000060
);
flush_work
(
&
ppwr
->
recv
.
work
);
return
nouveau_subdev_fini
(
&
ppwr
->
base
,
suspend
);
}
int
_nouveau_pwr_init
(
struct
nouveau_object
*
object
)
{
struct
nouveau_pwr
*
ppwr
=
(
void
*
)
object
;
int
ret
,
i
;
ret
=
nouveau_subdev_init
(
&
ppwr
->
base
);
if
(
ret
)
return
ret
;
nv_subdev
(
ppwr
)
->
intr
=
nouveau_pwr_intr
;
ppwr
->
message
=
nouveau_pwr_send
;
/* prevent previous ucode from running, wait for idle, reset */
nv_wr32
(
ppwr
,
0x10a014
,
0x0000ffff
);
/* INTR_EN_CLR = ALL */
nv_wait
(
ppwr
,
0x10a04c
,
0xffffffff
,
0x00000000
);
nv_mask
(
ppwr
,
0x000200
,
0x00002000
,
0x00000000
);
nv_mask
(
ppwr
,
0x000200
,
0x00002000
,
0x00002000
);
/* upload data segment */
nv_wr32
(
ppwr
,
0x10a1c0
,
0x01000000
);
for
(
i
=
0
;
i
<
ppwr
->
data
.
size
/
4
;
i
++
)
nv_wr32
(
ppwr
,
0x10a1c4
,
ppwr
->
data
.
data
[
i
]);
/* upload code segment */
nv_wr32
(
ppwr
,
0x10a180
,
0x01000000
);
for
(
i
=
0
;
i
<
ppwr
->
code
.
size
/
4
;
i
++
)
{
if
((
i
&
0x3f
)
==
0
)
nv_wr32
(
ppwr
,
0x10a188
,
i
>>
6
);
nv_wr32
(
ppwr
,
0x10a184
,
ppwr
->
code
.
data
[
i
]);
}
/* start it running */
nv_wr32
(
ppwr
,
0x10a10c
,
0x00000000
);
nv_wr32
(
ppwr
,
0x10a104
,
0x00000000
);
nv_wr32
(
ppwr
,
0x10a100
,
0x00000002
);
/* wait for valid host->pwr ring configuration */
if
(
!
nv_wait_ne
(
ppwr
,
0x10a4d0
,
0xffffffff
,
0x00000000
))
return
-
EBUSY
;
ppwr
->
send
.
base
=
nv_rd32
(
ppwr
,
0x10a4d0
)
&
0x0000ffff
;
ppwr
->
send
.
size
=
nv_rd32
(
ppwr
,
0x10a4d0
)
>>
16
;
/* wait for valid pwr->host ring configuration */
if
(
!
nv_wait_ne
(
ppwr
,
0x10a4dc
,
0xffffffff
,
0x00000000
))
return
-
EBUSY
;
ppwr
->
recv
.
base
=
nv_rd32
(
ppwr
,
0x10a4dc
)
&
0x0000ffff
;
ppwr
->
recv
.
size
=
nv_rd32
(
ppwr
,
0x10a4dc
)
>>
16
;
nv_wr32
(
ppwr
,
0x10a010
,
0x000000e0
);
return
0
;
}
int
nouveau_pwr_create_
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
int
length
,
void
**
pobject
)
{
struct
nouveau_pwr
*
ppwr
;
int
ret
;
ret
=
nouveau_subdev_create_
(
parent
,
engine
,
oclass
,
0
,
"PPWR"
,
"pwr"
,
length
,
pobject
);
ppwr
=
*
pobject
;
if
(
ret
)
return
ret
;
INIT_WORK
(
&
ppwr
->
recv
.
work
,
nouveau_pwr_recv
);
init_waitqueue_head
(
&
ppwr
->
recv
.
wait
);
return
0
;
}
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifdef INCLUDE_PROC
process(PROC_HOST, #host_init, #host_recv)
#endif
/******************************************************************************
* HOST data segment
*****************************************************************************/
#ifdef INCLUDE_DATA
// HOST (R)FIFO packet format
.equ #fifo_process 0x00
.equ #fifo_message 0x04
.equ #fifo_data0 0x08
.equ #fifo_data1 0x0c
// HOST HOST->PWR queue description
.equ #fifo_qlen 4 // log2(size of queue entry in bytes)
.equ #fifo_qnum 3 // log2(max number of entries in queue)
.equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue
.equ #fifo_qmaskp (#fifo_qmaskb - 1)
.equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1)
.equ #fifo_qsize (1 << (#fifo_qlen + #fifo_qnum))
fifo_queue: .skip 128 // #fifo_qsize
// HOST PWR->HOST queue description
.equ #rfifo_qlen 4 // log2(size of queue entry in bytes)
.equ #rfifo_qnum 3 // log2(max number of entries in queue)
.equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue
.equ #rfifo_qmaskp (#rfifo_qmaskb - 1)
.equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1)
.equ #rfifo_qsize (1 << (#rfifo_qlen + #rfifo_qnum))
rfifo_queue: .skip 128 // #rfifo_qsize
#endif
/******************************************************************************
* HOST code segment
*****************************************************************************/
#ifdef INCLUDE_CODE
// HOST->PWR comms - dequeue message(s) for process(es) from FIFO
//
// $r15 - current (host)
// $r0 - zero
host_send:
nv_iord($r1, NV_PPWR_FIFO_GET(0))
nv_iord($r2, NV_PPWR_FIFO_PUT(0))
cmp b32 $r1 $r2
bra e #host_send_done
// calculate address of message
and $r14 $r1 #fifo_qmaskp
shl b32 $r14 $r14 #fifo_qlen
add b32 $r14 #fifo_queue
// read message data, and pass to appropriate process
ld b32 $r11 D[$r14 + #fifo_data1]
ld b32 $r12 D[$r14 + #fifo_data0]
ld b32 $r13 D[$r14 + #fifo_message]
ld b32 $r14 D[$r14 + #fifo_process]
call(send)
// increment GET
add b32 $r1 0x1
and $r14 $r1 #fifo_qmaskf
nv_iowr(NV_PPWR_FIFO_GET(0), $r1)
bra #host_send
host_send_done:
ret
// PWR->HOST comms - enqueue message for HOST to RFIFO
//
// $r15 - current (host)
// $r14 - process
// $r13 - message
// $r12 - message data 0
// $r11 - message data 1
// $r0 - zero
host_recv:
// message from intr handler == HOST->PWR comms pending
mov $r1 (PROC_KERN & 0x0000ffff)
sethi $r1 (PROC_KERN & 0xffff0000)
cmp b32 $r14 $r1
bra e #host_send
// wait for space in RFIFO
host_recv_wait:
nv_iord($r1, NV_PPWR_RFIFO_GET)
nv_iord($r2, NV_PPWR_RFIFO_PUT)
xor $r1 #rfifo_qmaskb
cmp b32 $r1 $r2
bra e #host_recv_wait
and $r3 $r2 #rfifo_qmaskp
shl b32 $r3 #rfifo_qlen
add b32 $r3 #rfifo_queue
// enqueue message
st b32 D[$r3 + #fifo_data1] $r11
st b32 D[$r3 + #fifo_data0] $r12
st b32 D[$r3 + #fifo_message] $r13
st b32 D[$r3 + #fifo_process] $r14
add b32 $r2 0x1
and $r2 #rfifo_qmaskf
nv_iowr(NV_PPWR_RFIFO_PUT, $r2)
// notify host of pending message
mov $r2 NV_PPWR_INTR_TRIGGER_USER0
nv_iowr(NV_PPWR_INTR_TRIGGER, $r2)
ret
// $r15 - current (host)
// $r0 - zero
host_init:
// store each fifo's base/size in H2D/D2H scratch regs
mov $r1 #fifo_qsize
shl b32 $r1 16
or $r1 #fifo_queue
nv_iowr(NV_PPWR_H2D, $r1);
mov $r1 #rfifo_qsize
shl b32 $r1 16
or $r1 #rfifo_queue
nv_iowr(NV_PPWR_D2H, $r1);
// enable fifo subintr for first fifo
mov $r1 1
nv_iowr(NV_PPWR_FIFO_INTR_EN, $r1)
ret
#endif
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifdef INCLUDE_PROC
process(PROC_IDLE, #idle, #idle_recv)
#endif
/******************************************************************************
* IDLE data segment
*****************************************************************************/
#ifdef INCLUDE_DATA
#endif
/******************************************************************************
* IDLE code segment
*****************************************************************************/
#ifdef INCLUDE_CODE
// description
//
// $r15 - current (idle)
// $r14 - message
// $r0 - zero
idle_recv:
ret
// description
//
// $r15 - current (idle)
// $r0 - zero
idle:
// set our "no interrupt has occurred during our execution" flag
bset $flags $p0
// count IDLE invocations for debugging purposes
nv_iord($r1, NV_PPWR_DSCRATCH(1))
add b32 $r1 1
nv_iowr(NV_PPWR_DSCRATCH(1), $r1)
// keep looping while there's pending messages for any process
idle_loop:
mov $r1 #proc_list_head
bclr $flags $p2
idle_proc:
// process the process' messages until there's none left
idle_proc_exec:
push $r1
mov b32 $r14 $r1
call(recv)
pop $r1
bra not $p1 #idle_proc_next
bset $flags $p2
bra #idle_proc_exec
// next process!
idle_proc_next:
add b32 $r1 #proc_size
cmp b32 $r1 $r15
bra ne #idle_proc
bra $p2 #idle_loop
// sleep if no interrupts have occurred
sleep $p0
bra #idle
#endif
This diff is collapsed.
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
/******************************************************************************
* kernel data segment
*****************************************************************************/
#ifdef INCLUDE_PROC
proc_kern:
process(PROC_KERN, 0, 0)
proc_list_head:
#endif
#ifdef INCLUDE_DATA
proc_list_tail:
time_prev: .b32 0
time_next: .b32 0
#endif
/******************************************************************************
* kernel code segment
*****************************************************************************/
#ifdef INCLUDE_CODE
bra #init
// read nv register
//
// $r15 - current
// $r14 - addr
// $r13 - data (return)
// $r0 - zero
rd32:
nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
mov $r14 NV_PPWR_MMIO_CTRL_OP_RD
sethi $r14 NV_PPWR_MMIO_CTRL_TRIGGER
nv_iowr(NV_PPWR_MMIO_CTRL, $r14)
rd32_wait:
nv_iord($r14, NV_PPWR_MMIO_CTRL)
and $r14 NV_PPWR_MMIO_CTRL_STATUS
bra nz #rd32_wait
nv_iord($r13, NV_PPWR_MMIO_DATA)
ret
// write nv register
//
// $r15 - current
// $r14 - addr
// $r13 - data
// $r0 - zero
wr32:
nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
nv_iowr(NV_PPWR_MMIO_DATA, $r13)
mov $r14 NV_PPWR_MMIO_CTRL_OP_WR
or $r14 NV_PPWR_MMIO_CTRL_MASK_B32_0
sethi $r14 NV_PPWR_MMIO_CTRL_TRIGGER
#ifdef NVKM_FALCON_MMIO_TRAP
mov $r8 NV_PPWR_INTR_TRIGGER_USER1
nv_iowr(NV_PPWR_INTR_TRIGGER, $r8)
wr32_host:
nv_iord($r8, NV_PPWR_INTR)
and $r8 NV_PPWR_INTR_USER1
bra nz #wr32_host
#endif
nv_iowr(NV_PPWR_MMIO_CTRL, $r14)
wr32_wait:
nv_iord($r14, NV_PPWR_MMIO_CTRL)
and $r14 NV_PPWR_MMIO_CTRL_STATUS
bra nz #wr32_wait
ret
// busy-wait for a period of time
//
// $r15 - current
// $r14 - ns
// $r0 - zero
nsec:
nv_iord($r8, NV_PPWR_TIMER_LOW)
nsec_loop:
nv_iord($r9, NV_PPWR_TIMER_LOW)
sub b32 $r9 $r8
cmp b32 $r9 $r14
bra l #nsec_loop
ret
// busy-wait for a period of time
//
// $r15 - current
// $r14 - addr
// $r13 - mask
// $r12 - data
// $r11 - timeout (ns)
// $r0 - zero
wait:
nv_iord($r8, NV_PPWR_TIMER_LOW)
wait_loop:
nv_rd32($r10, $r14)
and $r10 $r13
cmp b32 $r10 $r12
bra e #wait_done
nv_iord($r9, NV_PPWR_TIMER_LOW)
sub b32 $r9 $r8
cmp b32 $r9 $r11
bra l #wait_loop
wait_done:
ret
// $r15 - current (kern)
// $r14 - process
// $r8 - NV_PPWR_INTR
intr_watchdog:
// read process' timer status, skip if not enabled
ld b32 $r9 D[$r14 + #proc_time]
cmp b32 $r9 0
bra z #intr_watchdog_next_proc
// subtract last timer's value from process' timer,
// if it's <= 0 then the timer has expired
ld b32 $r10 D[$r0 + #time_prev]
sub b32 $r9 $r10
bra g #intr_watchdog_next_time
mov $r13 KMSG_ALARM
call(send_proc)
clear b32 $r9
bra #intr_watchdog_next_proc
// otherwise, update the next timer's value if this
// process' timer is the soonest
intr_watchdog_next_time:
// ... or if there's no next timer yet
ld b32 $r10 D[$r0 + #time_next]
cmp b32 $r10 0
bra z #intr_watchdog_next_time_set
cmp b32 $r9 $r10
bra g #intr_watchdog_next_proc
intr_watchdog_next_time_set:
st b32 D[$r0 + #time_next] $r9
// update process' timer status, and advance
intr_watchdog_next_proc:
st b32 D[$r14 + #proc_time] $r9
add b32 $r14 #proc_size
cmp b32 $r14 #proc_list_tail
bra ne #intr_watchdog
ret
intr:
push $r0
clear b32 $r0
push $r8
push $r9
push $r10
push $r11
push $r12
push $r13
push $r14
push $r15
mov $r15 #proc_kern
mov $r8 $flags
push $r8
nv_iord($r8, NV_PPWR_DSCRATCH(0))
add b32 $r8 1
nv_iowr(NV_PPWR_DSCRATCH(0), $r8)
nv_iord($r8, NV_PPWR_INTR)
and $r9 $r8 NV_PPWR_INTR_WATCHDOG
bra z #intr_skip_watchdog
st b32 D[$r0 + #time_next] $r0
mov $r14 #proc_list_head
call(intr_watchdog)
ld b32 $r9 D[$r0 + #time_next]
cmp b32 $r9 0
bra z #intr_skip_watchdog
nv_iowr(NV_PPWR_WATCHDOG_TIME, $r9)
st b32 D[$r0 + #time_prev] $r9
intr_skip_watchdog:
and $r9 $r8 NV_PPWR_INTR_SUBINTR
bra z #intr_skip_subintr
nv_iord($r9, NV_PPWR_SUBINTR)
and $r10 $r9 NV_PPWR_SUBINTR_FIFO
bra z #intr_subintr_skip_fifo
nv_iord($r12, NV_PPWR_FIFO_INTR)
push $r12
mov $r14 (PROC_HOST & 0x0000ffff)
sethi $r14 (PROC_HOST & 0xffff0000)
mov $r13 KMSG_FIFO
call(send)
pop $r12
nv_iowr(NV_PPWR_FIFO_INTR, $r12)
intr_subintr_skip_fifo:
nv_iowr(NV_PPWR_SUBINTR, $r9)
intr_skip_subintr:
and $r9 $r8 NV_PPWR_INTR_PAUSE
bra z #intr_skip_pause
and $r10 0xffbf
intr_skip_pause:
and $r9 $r8 NV_PPWR_INTR_USER0
bra z #intr_skip_user0
and $r10 0xffbf
intr_skip_user0:
nv_iowr(NV_PPWR_INTR_ACK, $r8)
pop $r8
mov $flags $r8
pop $r15
pop $r14
pop $r13
pop $r12
pop $r11
pop $r10
pop $r9
pop $r8
pop $r0
bclr $flags $p0
iret
// request the current process be sent a message after a timeout expires
//
// $r15 - current
// $r14 - ticks
// $r0 - zero
timer:
// interrupts off to prevent racing with timer isr
bclr $flags ie0
// if current process already has a timer set, bail
ld b32 $r8 D[$r15 + #proc_time]
cmp b32 $r8 0
bra g #timer_done
st b32 D[$r15 + #proc_time] $r14
// halt watchdog timer temporarily and check for a pending
// interrupt. if there's one already pending, we can just
// bail since the timer isr will queue the next soonest
// right after it's done
nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8)
nv_iord($r8, NV_PPWR_INTR)
and $r8 NV_PPWR_INTR_WATCHDOG
bra nz #timer_enable
// update the watchdog if this timer should expire first,
// or if there's no timeout already set
nv_iord($r8, NV_PPWR_WATCHDOG_TIME)
cmp b32 $r14 $r0
bra e #timer_reset
cmp b32 $r14 $r8
bra l #timer_done
timer_reset:
nv_iowr(NV_PPWR_WATCHDOG_TIME, $r14)
st b32 D[$r0 + #time_prev] $r14
// re-enable the watchdog timer
timer_enable:
mov $r8 1
nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8)
// interrupts back on
timer_done:
bset $flags ie0
ret
// send message to another process
//
// $r15 - current
// $r14 - process
// $r13 - message
// $r12 - message data 0
// $r11 - message data 1
// $r0 - zero
send_proc:
push $r8
push $r9
// check for space in queue
ld b32 $r8 D[$r14 + #proc_qget]
ld b32 $r9 D[$r14 + #proc_qput]
xor $r8 #proc_qmaskb
cmp b32 $r8 $r9
bra e #send_done
// enqueue message
and $r8 $r9 #proc_qmaskp
shl b32 $r8 $r8 #proc_qlen
add b32 $r8 #proc_queue
add b32 $r8 $r14
ld b32 $r10 D[$r15 + #proc_id]
st b32 D[$r8 + #msg_process] $r10
st b32 D[$r8 + #msg_message] $r13
st b32 D[$r8 + #msg_data0] $r12
st b32 D[$r8 + #msg_data1] $r11
// increment PUT
add b32 $r9 1
and $r9 #proc_qmaskf
st b32 D[$r14 + #proc_qput] $r9
bset $flags $p2
send_done:
pop $r9
pop $r8
ret
// lookup process structure by its name
//
// $r15 - current
// $r14 - process name
// $r0 - zero
//
// $r14 - process
// $p1 - success
find:
push $r8
mov $r8 #proc_list_head
bset $flags $p1
find_loop:
ld b32 $r10 D[$r8 + #proc_id]
cmp b32 $r10 $r14
bra e #find_done
add b32 $r8 #proc_size
cmp b32 $r8 #proc_list_tail
bra ne #find_loop
bclr $flags $p1
find_done:
mov b32 $r14 $r8
pop $r8
ret
// send message to another process
//
// $r15 - current
// $r14 - process id
// $r13 - message
// $r12 - message data 0
// $r11 - message data 1
// $r0 - zero
send:
call(find)
bra $p1 #send_proc
ret
// process single message for a given process
//
// $r15 - current
// $r14 - process
// $r0 - zero
recv:
ld b32 $r8 D[$r14 + #proc_qget]
ld b32 $r9 D[$r14 + #proc_qput]
bclr $flags $p1
cmp b32 $r8 $r9
bra e #recv_done
// dequeue message
and $r9 $r8 #proc_qmaskp
add b32 $r8 1
and $r8 #proc_qmaskf
st b32 D[$r14 + #proc_qget] $r8
ld b32 $r10 D[$r14 + #proc_recv]
push $r15
mov $r15 $flags
push $r15
mov b32 $r15 $r14
shl b32 $r9 $r9 #proc_qlen
add b32 $r14 $r9
add b32 $r14 #proc_queue
ld b32 $r11 D[$r14 + #msg_data1]
ld b32 $r12 D[$r14 + #msg_data0]
ld b32 $r13 D[$r14 + #msg_message]
ld b32 $r14 D[$r14 + #msg_process]
// process it
call $r10
pop $r15
mov $flags $r15
bset $flags $p1
pop $r15
recv_done:
ret
init:
// setup stack
nv_iord($r1, NV_PPWR_CAPS)
extr $r1 $r1 9:17
shl b32 $r1 8
mov $sp $r1
#ifdef NVKM_FALCON_MMIO_UAS
// somehow allows the magic "access mmio via D[]" stuff that's
// used by the nv_rd32/nv_wr32 macros to work
mov $r1 0x0010
sethi $r1 NV_PPWR_UAS_CONFIG_ENABLE
nv_iowrs(NV_PPWR_UAS_CONFIG, $r1)
#endif
// route all interrupts except user0/1 and pause to fuc
mov $r1 0x00e0
sethi $r1 0x00000000
nv_iowr(NV_PPWR_INTR_ROUTE, $r1)
// enable watchdog and subintr intrs
mov $r1 NV_PPWR_INTR_EN_CLR_MASK
nv_iowr(NV_PPWR_INTR_EN_CLR, $r1)
mov $r1 NV_PPWR_INTR_EN_SET_WATCHDOG
or $r1 NV_PPWR_INTR_EN_SET_SUBINTR
nv_iowr(NV_PPWR_INTR_EN_SET, $r1)
// enable interrupts globally
mov $r1 #intr
sethi $r1 0x00000000
mov $iv0 $r1
bset $flags ie0
// enable watchdog timer
mov $r1 1
nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r1)
// bootstrap processes, idle process will be last, and not return
mov $r15 #proc_list_head
init_proc:
ld b32 $r1 D[$r15 + #proc_init]
cmp b32 $r1 0
bra z #init_proc
call $r1
add b32 $r15 #proc_size
bra #init_proc
#endif
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#define GT215 0xa3
#define GF100 0xc0
#define GF119 0xd9
#define GK208 0x108
#include "os.h"
// IO addresses
#define NV_PPWR_INTR_TRIGGER 0x0000
#define NV_PPWR_INTR_TRIGGER_USER1 0x00000080
#define NV_PPWR_INTR_TRIGGER_USER0 0x00000040
#define NV_PPWR_INTR_ACK 0x0004
#define NV_PPWR_INTR_ACK_SUBINTR 0x00000800
#define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002
#define NV_PPWR_INTR 0x0008
#define NV_PPWR_INTR_SUBINTR 0x00000800
#define NV_PPWR_INTR_USER1 0x00000080
#define NV_PPWR_INTR_USER0 0x00000040
#define NV_PPWR_INTR_PAUSE 0x00000020
#define NV_PPWR_INTR_WATCHDOG 0x00000002
#define NV_PPWR_INTR_EN_SET 0x0010
#define NV_PPWR_INTR_EN_SET_SUBINTR 0x00000800
#define NV_PPWR_INTR_EN_SET_WATCHDOG 0x00000002
#define NV_PPWR_INTR_EN_CLR 0x0014
#define NV_PPWR_INTR_EN_CLR_MASK /* fuck i hate envyas */ -1
#define NV_PPWR_INTR_ROUTE 0x001c
#define NV_PPWR_TIMER_LOW 0x002c
#define NV_PPWR_WATCHDOG_TIME 0x0034
#define NV_PPWR_WATCHDOG_ENABLE 0x0038
#define NV_PPWR_CAPS 0x0108
#define NV_PPWR_UAS_CONFIG 0x0164
#define NV_PPWR_UAS_CONFIG_ENABLE 0x00010000
#if NVKM_PPWR_CHIPSET >= GK208
#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x0450)
#endif
#define NV_PPWR_FIFO_PUT(i) (4 * (i) + 0x04a0)
#define NV_PPWR_FIFO_GET(i) (4 * (i) + 0x04b0)
#define NV_PPWR_FIFO_INTR 0x04c0
#define NV_PPWR_FIFO_INTR_EN 0x04c4
#define NV_PPWR_RFIFO_PUT 0x04c8
#define NV_PPWR_RFIFO_GET 0x04cc
#define NV_PPWR_H2D 0x04d0
#define NV_PPWR_D2H 0x04dc
#if NVKM_PPWR_CHIPSET < GK208
#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0)
#endif
#define NV_PPWR_SUBINTR 0x0688
#define NV_PPWR_SUBINTR_FIFO 0x00000002
#define NV_PPWR_MMIO_ADDR 0x07a0
#define NV_PPWR_MMIO_DATA 0x07a4
#define NV_PPWR_MMIO_CTRL 0x07ac
#define NV_PPWR_MMIO_CTRL_TRIGGER 0x00010000
#define NV_PPWR_MMIO_CTRL_STATUS 0x00007000
#define NV_PPWR_MMIO_CTRL_STATUS_IDLE 0x00000000
#define NV_PPWR_MMIO_CTRL_MASK 0x000000f0
#define NV_PPWR_MMIO_CTRL_MASK_B32_0 0x000000f0
#define NV_PPWR_MMIO_CTRL_OP 0x00000003
#define NV_PPWR_MMIO_CTRL_OP_RD 0x00000001
#define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002
#define NV_PPWR_OUTPUT 0x07c0
#define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004
#define NV_PPWR_OUTPUT_SET 0x07e0
#define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004
#define NV_PPWR_OUTPUT_CLR 0x07e4
#define NV_PPWR_OUTPUT_CLR_FB_PAUSE 0x00000004
// Inter-process message format
.equ #msg_process 0x00 /* send() target, recv() sender */
.equ #msg_message 0x04
.equ #msg_data0 0x08
.equ #msg_data1 0x0c
// Kernel message IDs
#define KMSG_FIFO 0x00000000
#define KMSG_ALARM 0x00000001
// Process message queue description
.equ #proc_qlen 4 // log2(size of queue entry in bytes)
.equ #proc_qnum 2 // log2(max number of entries in queue)
.equ #proc_qmaskb (1 << #proc_qnum) // max number of entries in queue
.equ #proc_qmaskp (#proc_qmaskb - 1)
.equ #proc_qmaskf ((#proc_qmaskb << 1) - 1)
.equ #proc_qsize (1 << (#proc_qlen + #proc_qnum))
// Process table entry
.equ #proc_id 0x00
.equ #proc_init 0x04
.equ #proc_recv 0x08
.equ #proc_time 0x0c
.equ #proc_qput 0x10
.equ #proc_qget 0x14
.equ #proc_queue 0x18
.equ #proc_size (0x18 + #proc_qsize)
#define process(id,init,recv) /*
*/ .b32 id /*
*/ .b32 init /*
*/ .b32 recv /*
*/ .b32 0 /*
*/ .b32 0 /*
*/ .b32 0 /*
*/ .skip 64
#ifndef NVKM_FALCON_UNSHIFTED_IO
#define nv_iord(reg,ior) /*
*/ mov reg ior /*
*/ shl b32 reg 6 /*
*/ iord reg I[reg + 0x000]
#else
#define nv_iord(reg,ior) /*
*/ mov reg ior /*
*/ iord reg I[reg + 0x000]
#endif
#ifndef NVKM_FALCON_UNSHIFTED_IO
#define nv_iowr(ior,reg) /*
*/ mov $r0 ior /*
*/ shl b32 $r0 6 /*
*/ iowr I[$r0 + 0x000] reg /*
*/ clear b32 $r0
#else
#define nv_iowr(ior,reg) /*
*/ mov $r0 ior /*
*/ iowr I[$r0 + 0x000] reg /*
*/ clear b32 $r0
#endif
#ifndef NVKM_FALCON_UNSHIFTED_IO
#define nv_iowrs(ior,reg) /*
*/ mov $r0 ior /*
*/ shl b32 $r0 6 /*
*/ iowrs I[$r0 + 0x000] reg /*
*/ clear b32 $r0
#else
#define nv_iowrs(ior,reg) /*
*/ mov $r0 ior /*
*/ iowrs I[$r0 + 0x000] reg /*
*/ clear b32 $r0
#endif
#define hash #
#define fn(a) a
#ifndef NVKM_FALCON_PC24
#define call(a) call fn(hash)a
#else
#define call(a) lcall fn(hash)a
#endif
#ifndef NVKM_FALCON_MMIO_UAS
#define nv_rd32(reg,addr) /*
*/ mov b32 $r14 addr /*
*/ call(rd32) /*
*/ mov b32 reg $r13
#else
#define nv_rd32(reg,addr) /*
*/ sethi $r0 0x14000000 /*
*/ or $r0 addr /*
*/ ld b32 reg D[$r0] /*
*/ clear b32 $r0
#endif
#if !defined(NVKM_FALCON_MMIO_UAS) || defined(NVKM_FALCON_MMIO_TRAP)
#define nv_wr32(addr,reg) /*
*/ push addr /*
*/ push reg /*
*/ pop $r13 /*
*/ pop $r14 /*
*/ call(wr32) /*
#else
#define nv_wr32(addr,reg) /*
*/ sethi $r0 0x14000000 /*
*/ or $r0 addr /*
*/ st b32 D[$r0] reg /*
*/ clear b32 $r0
#endif
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifdef INCLUDE_PROC
process(PROC_MEMX, #memx_init, #memx_recv)
#endif
/******************************************************************************
* MEMX data segment
*****************************************************************************/
#ifdef INCLUDE_DATA
.equ #memx_opcode 0
.equ #memx_header 2
.equ #memx_length 4
.equ #memx_func 8
#define handler(cmd,hdr,len,func) /*
*/ .b16 MEMX_##cmd /*
*/ .b16 hdr /*
*/ .b16 len /*
*/ .b16 0 /*
*/ .b32 func
memx_func_head:
handler(ENTER , 0x0001, 0x0000, #memx_func_enter)
memx_func_next:
handler(LEAVE , 0x0000, 0x0000, #memx_func_leave)
handler(WR32 , 0x0000, 0x0002, #memx_func_wr32)
handler(WAIT , 0x0004, 0x0000, #memx_func_wait)
handler(DELAY , 0x0001, 0x0000, #memx_func_delay)
memx_func_tail:
.equ #memx_func_size #memx_func_next - #memx_func_head
.equ #memx_func_num (#memx_func_tail - #memx_func_head) / #memx_func_size
memx_data_head:
.skip 0x0800
memx_data_tail:
#endif
/******************************************************************************
* MEMX code segment
*****************************************************************************/
#ifdef INCLUDE_CODE
// description
//
// $r15 - current (memx)
// $r4 - packet length
// +00: bitmask of heads to wait for vblank on
// $r3 - opcode desciption
// $r0 - zero
memx_func_enter:
mov $r6 NV_PPWR_OUTPUT_SET_FB_PAUSE
nv_iowr(NV_PPWR_OUTPUT_SET, $r6)
memx_func_enter_wait:
nv_iord($r6, NV_PPWR_OUTPUT)
and $r6 NV_PPWR_OUTPUT_FB_PAUSE
bra z #memx_func_enter_wait
//XXX: TODO
ld b32 $r6 D[$r1 + 0x00]
add b32 $r1 0x04
ret
// description
//
// $r15 - current (memx)
// $r4 - packet length
// $r3 - opcode desciption
// $r0 - zero
memx_func_leave:
mov $r6 NV_PPWR_OUTPUT_CLR_FB_PAUSE
nv_iowr(NV_PPWR_OUTPUT_CLR, $r6)
memx_func_leave_wait:
nv_iord($r6, NV_PPWR_OUTPUT)
and $r6 NV_PPWR_OUTPUT_FB_PAUSE
bra nz #memx_func_leave_wait
ret
// description
//
// $r15 - current (memx)
// $r4 - packet length
// +00*n: addr
// +04*n: data
// $r3 - opcode desciption
// $r0 - zero
memx_func_wr32:
ld b32 $r6 D[$r1 + 0x00]
ld b32 $r5 D[$r1 + 0x04]
add b32 $r1 0x08
nv_wr32($r6, $r5)
sub b32 $r4 0x02
bra nz #memx_func_wr32
ret
// description
//
// $r15 - current (memx)
// $r4 - packet length
// +00: addr
// +04: mask
// +08: data
// +0c: timeout (ns)
// $r3 - opcode desciption
// $r0 - zero
memx_func_wait:
nv_iord($r8, NV_PPWR_TIMER_LOW)
ld b32 $r14 D[$r1 + 0x00]
ld b32 $r13 D[$r1 + 0x04]
ld b32 $r12 D[$r1 + 0x08]
ld b32 $r11 D[$r1 + 0x0c]
add b32 $r1 0x10
call(wait)
ret
// description
//
// $r15 - current (memx)
// $r4 - packet length
// +00: time (ns)
// $r3 - opcode desciption
// $r0 - zero
memx_func_delay:
ld b32 $r14 D[$r1 + 0x00]
add b32 $r1 0x04
call(nsec)
ret
// description
//
// $r15 - current (memx)
// $r14 - sender process name
// $r13 - message (exec)
// $r12 - head of script
// $r11 - tail of script
// $r0 - zero
memx_exec:
push $r14
push $r13
mov b32 $r1 $r12
mov b32 $r2 $r11
memx_exec_next:
// fetch the packet header, and locate opcode info
ld b32 $r3 D[$r1]
add b32 $r1 4
shr b32 $r4 $r3 16
mulu $r3 #memx_func_size
// execute the opcode handler
ld b32 $r5 D[$r3 + #memx_func_head + #memx_func]
call $r5
// keep going, if we haven't reached the end
cmp b32 $r1 $r2
bra l #memx_exec_next
// send completion reply
pop $r13
pop $r14
call(send)
ret
// description
//
// $r15 - current (memx)
// $r14 - sender process name
// $r13 - message
// $r12 - data0
// $r11 - data1
// $r0 - zero
memx_info:
mov $r12 #memx_data_head
mov $r11 #memx_data_tail - #memx_data_head
call(send)
ret
// description
//
// $r15 - current (memx)
// $r14 - sender process name
// $r13 - message
// $r12 - data0
// $r11 - data1
// $r0 - zero
memx_recv:
cmp b32 $r13 MEMX_MSG_EXEC
bra e #memx_exec
cmp b32 $r13 MEMX_MSG_INFO
bra e #memx_info
ret
// description
//
// $r15 - current (memx)
// $r0 - zero
memx_init:
ret
#endif
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#define NVKM_PPWR_CHIPSET GK208
#define NVKM_FALCON_PC24
#define NVKM_FALCON_UNSHIFTED_IO
//#define NVKM_FALCON_MMIO_UAS
//#define NVKM_FALCON_MMIO_TRAP
#include "macros.fuc"
.section #nv108_pwr_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_PROC
#define INCLUDE_DATA
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_DATA
.align 256
.section #nv108_pwr_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_CODE
.align 256
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
0 → 100644
浏览文件 @
ff4b42c7
uint32_t
nv108_pwr_data
[]
=
{
/* 0x0000: proc_kern */
0x52544e49
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0058: proc_list_head */
0x54534f48
,
0x00000379
,
0x0000032a
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x584d454d
,
0x0000046f
,
0x00000461
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x46524550
,
0x00000473
,
0x00000471
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x54534554
,
0x00000494
,
0x00000475
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x454c4449
,
0x0000049f
,
0x0000049d
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0210: proc_list_tail */
/* 0x0210: time_prev */
0x00000000
,
/* 0x0214: time_next */
0x00000000
,
/* 0x0218: fifo_queue */
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0298: rfifo_queue */
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0318: memx_func_head */
0x00010000
,
0x00000000
,
0x000003a9
,
/* 0x0324: memx_func_next */
0x00000001
,
0x00000000
,
0x000003c7
,
0x00000002
,
0x00000002
,
0x000003df
,
0x00040003
,
0x00000000
,
0x00000407
,
0x00010004
,
0x00000000
,
0x00000421
,
/* 0x0354: memx_func_tail */
/* 0x0354: memx_data_head */
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0b54: memx_data_tail */
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
};
uint32_t
nv108_pwr_code
[]
=
{
0x02910ef5
,
/* 0x0004: rd32 */
0xf607a040
,
0x04bd000e
,
0xe3f0010e
,
0x07ac4001
,
0xbd000ef6
,
/* 0x0019: rd32_wait */
0x07ac4e04
,
0xf100eecf
,
0xf47000e4
,
0xa44df61b
,
0x00ddcf07
,
/* 0x002e: wr32 */
0xa04000f8
,
0x000ef607
,
0xa44004bd
,
0x000df607
,
0x020e04bd
,
0xf0f0e5f0
,
0xac4001e3
,
0x000ef607
,
/* 0x004e: wr32_wait */
0xac4e04bd
,
0x00eecf07
,
0x7000e4f1
,
0xf8f61bf4
,
/* 0x005d: nsec */
0xcf2c0800
,
/* 0x0062: nsec_loop */
0x2c090088
,
0xbb0099cf
,
0x9ea60298
,
0xf8f61ef4
,
/* 0x0071: wait */
0xcf2c0800
,
/* 0x0076: wait_loop */
0xeeb20088
,
0x0000047e
,
0xadfddab2
,
0xf4aca604
,
0x2c09100b
,
0xbb0099cf
,
0x9ba60298
,
/* 0x0093: wait_done */
0xf8e61ef4
,
/* 0x0095: intr_watchdog */
0x03e99800
,
0xf40096b0
,
0x0a98280b
,
0x029abb84
,
0x0d0e1cf4
,
0x01de7e01
,
0xf494bd00
,
/* 0x00b2: intr_watchdog_next_time */
0x0a98140e
,
0x00a6b085
,
0xa6080bf4
,
0x061cf49a
,
/* 0x00c0: intr_watchdog_next_time_set */
/* 0x00c3: intr_watchdog_next_proc */
0xb58509b5
,
0xe0b603e9
,
0x10e6b158
,
0xc81bf402
,
/* 0x00d2: intr */
0x00f900f8
,
0x80f904bd
,
0xa0f990f9
,
0xc0f9b0f9
,
0xe0f9d0f9
,
0x000ff0f9
,
0xf90188fe
,
0x04504880
,
0xb60088cf
,
0x50400180
,
0x0008f604
,
0x080804bd
,
0xc40088cf
,
0x0bf40289
,
0x8500b51f
,
0x957e580e
,
0x09980000
,
0x0096b085
,
0x000d0bf4
,
0x0009f634
,
0x09b504bd
,
/* 0x0125: intr_skip_watchdog */
0x0089e484
,
0x360bf408
,
0xcf068849
,
0x9ac40099
,
0x220bf402
,
0xcf04c04c
,
0xc0f900cc
,
0xf14f484e
,
0x0d5453e3
,
0x023f7e00
,
0x40c0fc00
,
0x0cf604c0
,
/* 0x0157: intr_subintr_skip_fifo */
0x4004bd00
,
0x09f60688
,
/* 0x015f: intr_skip_subintr */
0xc404bd00
,
0x0bf42089
,
0xbfa4f107
,
/* 0x0169: intr_skip_pause */
0x4089c4ff
,
0xf1070bf4
,
/* 0x0173: intr_skip_user0 */
0x00ffbfa4
,
0x0008f604
,
0x80fc04bd
,
0xfc0088fe
,
0xfce0fcf0
,
0xfcc0fcd0
,
0xfca0fcb0
,
0xfc80fc90
,
0x0032f400
,
/* 0x0196: timer */
0x32f401f8
,
0x03f89810
,
0xf40086b0
,
0xfeb53a1c
,
0xf6380003
,
0x04bd0008
,
0x88cf0808
,
0x0284f000
,
0x081c1bf4
,
0x0088cf34
,
0x0bf4e0a6
,
0xf4e8a608
,
/* 0x01c6: timer_reset */
0x3400161e
,
0xbd000ef6
,
0x840eb504
,
/* 0x01d0: timer_enable */
0x38000108
,
0xbd0008f6
,
/* 0x01d9: timer_done */
0x1031f404
,
/* 0x01de: send_proc */
0x80f900f8
,
0xe89890f9
,
0x04e99805
,
0xa60486f0
,
0x2a0bf489
,
0x940398c4
,
0x80b60488
,
0x008ebb18
,
0xb500fa98
,
0x8db5008a
,
0x028cb501
,
0xb6038bb5
,
0x94f00190
,
0x04e9b507
,
/* 0x0217: send_done */
0xfc0231f4
,
0xf880fc90
,
/* 0x021d: find */
0x0880f900
,
0x0131f458
,
/* 0x0224: find_loop */
0xa6008a98
,
0x100bf4ae
,
0xb15880b6
,
0xf4021086
,
0x32f4f11b
,
/* 0x0239: find_done */
0xfc8eb201
,
/* 0x023f: send */
0x7e00f880
,
0xf400021d
,
0x00f89b01
,
/* 0x0248: recv */
0x9805e898
,
0x32f404e9
,
0xf489a601
,
0x89c43c0b
,
0x0180b603
,
0xb50784f0
,
0xea9805e8
,
0xfef0f902
,
0xf0f9018f
,
0x9994efb2
,
0x00e9bb04
,
0x9818e0b6
,
0xec9803eb
,
0x01ed9802
,
0xf900ee98
,
0xfef0fca5
,
0x31f400f8
,
/* 0x028f: recv_done */
0xf8f0fc01
,
/* 0x0291: init */
0x01084100
,
0xe70011cf
,
0xb6010911
,
0x14fe0814
,
0x00e04100
,
0x000013f0
,
0x0001f61c
,
0xff0104bd
,
0x01f61400
,
0x0104bd00
,
0x0015f102
,
0xf6100008
,
0x04bd0001
,
0xf000d241
,
0x10fe0013
,
0x1031f400
,
0x38000101
,
0xbd0001f6
,
/* 0x02db: init_proc */
0x98580f04
,
0x16b001f1
,
0xfa0bf400
,
0xf0b615f9
,
0xf20ef458
,
/* 0x02ec: host_send */
0xcf04b041
,
0xa0420011
,
0x0022cf04
,
0x0bf412a6
,
0x071ec42e
,
0xb704ee94
,
0x980218e0
,
0xec9803eb
,
0x01ed9802
,
0x7e00ee98
,
0xb600023f
,
0x1ec40110
,
0x04b0400f
,
0xbd0001f6
,
0xc70ef404
,
/* 0x0328: host_send_done */
/* 0x032a: host_recv */
0x494100f8
,
0x5413f14e
,
0xf4e1a652
,
/* 0x0336: host_recv_wait */
0xcc41b90b
,
0x0011cf04
,
0xcf04c842
,
0x16f00022
,
0xf412a608
,
0x23c4ef0b
,
0x0434b607
,
0x029830b7
,
0xb5033bb5
,
0x3db5023c
,
0x003eb501
,
0xf00120b6
,
0xc8400f24
,
0x0002f604
,
0x400204bd
,
0x02f60000
,
0xf804bd00
,
/* 0x0379: host_init */
0x00804100
,
0xf11014b6
,
0x40021815
,
0x01f604d0
,
0x4104bd00
,
0x14b60080
,
0x9815f110
,
0x04dc4002
,
0xbd0001f6
,
0x40010104
,
0x01f604c4
,
0xf804bd00
,
/* 0x03a9: memx_func_enter */
0x40040600
,
0x06f607e0
,
/* 0x03b3: memx_func_enter_wait */
0x4604bd00
,
0x66cf07c0
,
0x0464f000
,
0x98f70bf4
,
0x10b60016
,
/* 0x03c7: memx_func_leave */
0x0600f804
,
0x07e44004
,
0xbd0006f6
,
/* 0x03d1: memx_func_leave_wait */
0x07c04604
,
0xf00066cf
,
0x1bf40464
,
/* 0x03df: memx_func_wr32 */
0x9800f8f7
,
0x15980016
,
0x0810b601
,
0x50f960f9
,
0xe0fcd0fc
,
0x00002e7e
,
0x140003f1
,
0xa00506fd
,
0xb604bd05
,
0x1bf40242
,
/* 0x0407: memx_func_wait */
0x0800f8dd
,
0x0088cf2c
,
0x98001e98
,
0x1c98011d
,
0x031b9802
,
0x7e1010b6
,
0xf8000071
,
/* 0x0421: memx_func_delay */
0x001e9800
,
0x7e0410b6
,
0xf800005d
,
/* 0x042d: memx_exec */
0xf9e0f900
,
0xb2c1b2d0
,
/* 0x0435: memx_exec_next */
0x001398b2
,
0x950410b6
,
0x30f01034
,
0xc835980c
,
0x12a655f9
,
0xfced1ef4
,
0x7ee0fcd0
,
0xf800023f
,
/* 0x0455: memx_info */
0x03544c00
,
0x7e08004b
,
0xf800023f
,
/* 0x0461: memx_recv */
0x01d6b000
,
0xb0c90bf4
,
0x0bf400d6
,
/* 0x046f: memx_init */
0xf800f8eb
,
/* 0x0471: perf_recv */
/* 0x0473: perf_init */
0xf800f800
,
/* 0x0475: test_recv */
0x04584100
,
0xb60011cf
,
0x58400110
,
0x0001f604
,
0xe7f104bd
,
0xe3f1d900
,
0x967e134f
,
0x00f80001
,
/* 0x0494: test_init */
0x7e08004e
,
0xf8000196
,
/* 0x049d: idle_recv */
/* 0x049f: idle */
0xf400f800
,
0x54410031
,
0x0011cf04
,
0x400110b6
,
0x01f60454
,
/* 0x04b3: idle_loop */
0x0104bd00
,
0x0232f458
,
/* 0x04b8: idle_proc */
/* 0x04b8: idle_proc_exec */
0x1eb210f9
,
0x0002487e
,
0x11f410fc
,
0x0231f409
,
/* 0x04cb: idle_proc_next */
0xb6f00ef4
,
0x1fa65810
,
0xf4e81bf4
,
0x28f4e002
,
0xc60ef400
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
};
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#define NVKM_PPWR_CHIPSET GT215
//#define NVKM_FALCON_PC24
//#define NVKM_FALCON_UNSHIFTED_IO
//#define NVKM_FALCON_MMIO_UAS
//#define NVKM_FALCON_MMIO_TRAP
#include "macros.fuc"
.section #nva3_pwr_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_PROC
#define INCLUDE_DATA
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_DATA
.align 256
.section #nva3_pwr_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_CODE
.align 256
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
0 → 100644
浏览文件 @
ff4b42c7
uint32_t
nva3_pwr_data
[]
=
{
/* 0x0000: proc_kern */
0x52544e49
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0058: proc_list_head */
0x54534f48
,
0x00000430
,
0x000003cd
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x584d454d
,
0x0000054e
,
0x00000540
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x46524550
,
0x00000552
,
0x00000550
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x54534554
,
0x0000057b
,
0x00000554
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
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0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x454c4449
,
0x00000587
,
0x00000585
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0210: proc_list_tail */
/* 0x0210: time_prev */
0x00000000
,
/* 0x0214: time_next */
0x00000000
,
/* 0x0218: fifo_queue */
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0298: rfifo_queue */
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0318: memx_func_head */
0x00010000
,
0x00000000
,
0x0000046f
,
/* 0x0324: memx_func_next */
0x00000001
,
0x00000000
,
0x00000496
,
0x00000002
,
0x00000002
,
0x000004b7
,
0x00040003
,
0x00000000
,
0x000004df
,
0x00010004
,
0x00000000
,
0x000004fc
,
/* 0x0354: memx_func_tail */
/* 0x0354: memx_data_head */
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
,
0x00000000
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0x00000000
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0x00000000
,
0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
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0x00000000
,
0x00000000
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0x00000000
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0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
/* 0x0b54: memx_data_tail */
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
};
uint32_t
nva3_pwr_code
[]
=
{
0x030d0ef5
,
/* 0x0004: rd32 */
0x07a007f1
,
0xd00604b6
,
0x04bd000e
,
0xf001e7f0
,
0x07f101e3
,
0x04b607ac
,
0x000ed006
,
/* 0x0022: rd32_wait */
0xe7f104bd
,
0xe4b607ac
,
0x00eecf06
,
0x7000e4f1
,
0xf1f21bf4
,
0xb607a4d7
,
0xddcf06d4
,
/* 0x003f: wr32 */
0xf100f800
,
0xb607a007
,
0x0ed00604
,
0xf104bd00
,
0xb607a407
,
0x0dd00604
,
0xf004bd00
,
0xe5f002e7
,
0x01e3f0f0
,
0x07ac07f1
,
0xd00604b6
,
0x04bd000e
,
/* 0x006c: wr32_wait */
0x07ace7f1
,
0xcf06e4b6
,
0xe4f100ee
,
0x1bf47000
,
/* 0x007f: nsec */
0xf000f8f2
,
0x84b62c87
,
0x0088cf06
,
/* 0x0088: nsec_loop */
0xb62c97f0
,
0x99cf0694
,
0x0298bb00
,
0xf4069eb8
,
0x00f8f11e
,
/* 0x009c: wait */
0xb62c87f0
,
0x88cf0684
,
/* 0x00a5: wait_loop */
0x02eeb900
,
0xb90421f4
,
0xadfd02da
,
0x06acb804
,
0xf0150bf4
,
0x94b62c97
,
0x0099cf06
,
0xb80298bb
,
0x1ef4069b
,
/* 0x00c9: wait_done */
/* 0x00cb: intr_watchdog */
0x9800f8df
,
0x96b003e9
,
0x2a0bf400
,
0xbb840a98
,
0x1cf4029a
,
0x01d7f00f
,
0x025421f5
,
0x0ef494bd
,
/* 0x00e9: intr_watchdog_next_time */
0x850a9815
,
0xf400a6b0
,
0x9ab8090b
,
0x061cf406
,
/* 0x00f8: intr_watchdog_next_time_set */
/* 0x00fb: intr_watchdog_next_proc */
0x80850980
,
0xe0b603e9
,
0x10e6b158
,
0xc61bf402
,
/* 0x010a: intr */
0x00f900f8
,
0x80f904bd
,
0xa0f990f9
,
0xc0f9b0f9
,
0xe0f9d0f9
,
0xf7f0f0f9
,
0x0188fe00
,
0x87f180f9
,
0x84b605d0
,
0x0088cf06
,
0xf10180b6
,
0xb605d007
,
0x08d00604
,
0xf004bd00
,
0x84b60887
,
0x0088cf06
,
0xf40289c4
,
0x0080230b
,
0x58e7f085
,
0x98cb21f4
,
0x96b08509
,
0x110bf400
,
0xb63407f0
,
0x09d00604
,
0x8004bd00
,
/* 0x016e: intr_skip_watchdog */
0x89e48409
,
0x0bf40800
,
0x8897f148
,
0x0694b606
,
0xc40099cf
,
0x0bf4029a
,
0xc0c7f12c
,
0x06c4b604
,
0xf900cccf
,
0x48e7f1c0
,
0x53e3f14f
,
0x00d7f054
,
0x02b921f5
,
0x07f1c0fc
,
0x04b604c0
,
0x000cd006
,
/* 0x01ae: intr_subintr_skip_fifo */
0x07f104bd
,
0x04b60688
,
0x0009d006
,
/* 0x01ba: intr_skip_subintr */
0x89c404bd
,
0x070bf420
,
0xffbfa4f1
,
/* 0x01c4: intr_skip_pause */
0xf44089c4
,
0xa4f1070b
,
/* 0x01ce: intr_skip_user0 */
0x07f0ffbf
,
0x0604b604
,
0xbd0008d0
,
0xfe80fc04
,
0xf0fc0088
,
0xd0fce0fc
,
0xb0fcc0fc
,
0x90fca0fc
,
0x00fc80fc
,
0xf80032f4
,
/* 0x01f5: timer */
0x1032f401
,
0xb003f898
,
0x1cf40086
,
0x03fe8051
,
0xb63807f0
,
0x08d00604
,
0xf004bd00
,
0x84b60887
,
0x0088cf06
,
0xf40284f0
,
0x87f0261b
,
0x0684b634
,
0xb80088cf
,
0x0bf406e0
,
0x06e8b809
,
/* 0x0233: timer_reset */
0xf01f1ef4
,
0x04b63407
,
0x000ed006
,
0x0e8004bd
,
/* 0x0241: timer_enable */
0x0187f084
,
0xb63807f0
,
0x08d00604
,
/* 0x024f: timer_done */
0xf404bd00
,
0x00f81031
,
/* 0x0254: send_proc */
0x90f980f9
,
0x9805e898
,
0x86f004e9
,
0x0689b804
,
0xc42a0bf4
,
0x88940398
,
0x1880b604
,
0x98008ebb
,
0x8a8000fa
,
0x018d8000
,
0x80028c80
,
0x90b6038b
,
0x0794f001
,
0xf404e980
,
/* 0x028e: send_done */
0x90fc0231
,
0x00f880fc
,
/* 0x0294: find */
0x87f080f9
,
0x0131f458
,
/* 0x029c: find_loop */
0xb8008a98
,
0x0bf406ae
,
0x5880b610
,
0x021086b1
,
0xf4f01bf4
,
/* 0x02b2: find_done */
0x8eb90132
,
0xf880fc02
,
/* 0x02b9: send */
0x9421f500
,
0x9701f402
,
/* 0x02c2: recv */
0xe89800f8
,
0x04e99805
,
0xb80132f4
,
0x0bf40689
,
0x0389c43d
,
0xf00180b6
,
0xe8800784
,
0x02ea9805
,
0x8ffef0f9
,
0xb9f0f901
,
0x999402ef
,
0x00e9bb04
,
0x9818e0b6
,
0xec9803eb
,
0x01ed9802
,
0xf900ee98
,
0xfef0fca5
,
0x31f400f8
,
/* 0x030b: recv_done */
0xf8f0fc01
,
/* 0x030d: init */
0x0817f100
,
0x0614b601
,
0xe70011cf
,
0xb6010911
,
0x14fe0814
,
0xe017f100
,
0x0013f000
,
0xb61c07f0
,
0x01d00604
,
0xf004bd00
,
0x07f0ff17
,
0x0604b614
,
0xbd0001d0
,
0x0217f004
,
0x080015f1
,
0xb61007f0
,
0x01d00604
,
0xf104bd00
,
0xf0010a17
,
0x10fe0013
,
0x1031f400
,
0xf00117f0
,
0x04b63807
,
0x0001d006
,
0xf7f004bd
,
/* 0x0371: init_proc */
0x01f19858
,
0xf40016b0
,
0x15f9fa0b
,
0xf458f0b6
,
/* 0x0382: host_send */
0x17f1f20e
,
0x14b604b0
,
0x0011cf06
,
0x04a027f1
,
0xcf0624b6
,
0x12b80022
,
0x320bf406
,
0x94071ec4
,
0xe0b704ee
,
0xeb980218
,
0x02ec9803
,
0x9801ed98
,
0x21f500ee
,
0x10b602b9
,
0x0f1ec401
,
0x04b007f1
,
0xd00604b6
,
0x04bd0001
,
/* 0x03cb: host_send_done */
0xf8ba0ef4
,
/* 0x03cd: host_recv */
0x4917f100
,
0x5413f14e
,
0x06e1b852
,
/* 0x03db: host_recv_wait */
0xf1aa0bf4
,
0xb604cc17
,
0x11cf0614
,
0xc827f100
,
0x0624b604
,
0xf00022cf
,
0x12b80816
,
0xe60bf406
,
0xb60723c4
,
0x30b70434
,
0x3b800298
,
0x023c8003
,
0x80013d80
,
0x20b6003e
,
0x0f24f001
,
0x04c807f1
,
0xd00604b6
,
0x04bd0002
,
0xf04027f0
,
0x04b60007
,
0x0002d006
,
0x00f804bd
,
/* 0x0430: host_init */
0x008017f1
,
0xf11014b6
,
0xf1021815
,
0xb604d007
,
0x01d00604
,
0xf104bd00
,
0xb6008017
,
0x15f11014
,
0x07f10298
,
0x04b604dc
,
0x0001d006
,
0x17f004bd
,
0xc407f101
,
0x0604b604
,
0xbd0001d0
,
/* 0x046f: memx_func_enter */
0xf000f804
,
0x07f10467
,
0x04b607e0
,
0x0006d006
,
/* 0x047e: memx_func_enter_wait */
0x67f104bd
,
0x64b607c0
,
0x0066cf06
,
0xf40464f0
,
0x1698f30b
,
0x0410b600
,
/* 0x0496: memx_func_leave */
0x67f000f8
,
0xe407f104
,
0x0604b607
,
0xbd0006d0
,
/* 0x04a5: memx_func_leave_wait */
0xc067f104
,
0x0664b607
,
0xf00066cf
,
0x1bf40464
,
/* 0x04b7: memx_func_wr32 */
0x9800f8f3
,
0x15980016
,
0x0810b601
,
0x50f960f9
,
0xe0fcd0fc
,
0xf13f21f4
,
0xfd140003
,
0x05800506
,
0xb604bd00
,
0x1bf40242
,
/* 0x04df: memx_func_wait */
0xf000f8dd
,
0x84b62c87
,
0x0088cf06
,
0x98001e98
,
0x1c98011d
,
0x031b9802
,
0xf41010b6
,
0x00f89c21
,
/* 0x04fc: memx_func_delay */
0xb6001e98
,
0x21f40410
,
/* 0x0507: memx_exec */
0xf900f87f
,
0xb9d0f9e0
,
0xb2b902c1
,
/* 0x0511: memx_exec_next */
0x00139802
,
0x950410b6
,
0x30f01034
,
0xc835980c
,
0x12b855f9
,
0xec1ef406
,
0xe0fcd0fc
,
0x02b921f5
,
/* 0x0532: memx_info */
0xc7f100f8
,
0xb7f10354
,
0x21f50800
,
0x00f802b9
,
/* 0x0540: memx_recv */
0xf401d6b0
,
0xd6b0c40b
,
0xe90bf400
,
/* 0x054e: memx_init */
0x00f800f8
,
/* 0x0550: perf_recv */
/* 0x0552: perf_init */
0x00f800f8
,
/* 0x0554: test_recv */
0x05d817f1
,
0xcf0614b6
,
0x10b60011
,
0xd807f101
,
0x0604b605
,
0xbd0001d0
,
0x00e7f104
,
0x4fe3f1d9
,
0xf521f513
,
/* 0x057b: test_init */
0xf100f801
,
0xf50800e7
,
0xf801f521
,
/* 0x0585: idle_recv */
/* 0x0587: idle */
0xf400f800
,
0x17f10031
,
0x14b605d4
,
0x0011cf06
,
0xf10110b6
,
0xb605d407
,
0x01d00604
,
/* 0x05a3: idle_loop */
0xf004bd00
,
0x32f45817
,
/* 0x05a9: idle_proc */
/* 0x05a9: idle_proc_exec */
0xb910f902
,
0x21f5021e
,
0x10fc02c2
,
0xf40911f4
,
0x0ef40231
,
/* 0x05bd: idle_proc_next */
0x5810b6ef
,
0xf4061fb8
,
0x02f4e61b
,
0x0028f4dd
,
0x00bb0ef4
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
0x00000000
,
};
This diff is collapsed.
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#define NVKM_PPWR_CHIPSET GF100
//#define NVKM_FALCON_PC24
//#define NVKM_FALCON_UNSHIFTED_IO
//#define NVKM_FALCON_MMIO_UAS
//#define NVKM_FALCON_MMIO_TRAP
#include "macros.fuc"
.section #nvc0_pwr_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_PROC
#define INCLUDE_DATA
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_DATA
.align 256
.section #nvc0_pwr_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_CODE
.align 256
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
0 → 100644
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#define NVKM_PPWR_CHIPSET GF119
//#define NVKM_FALCON_PC24
#define NVKM_FALCON_UNSHIFTED_IO
//#define NVKM_FALCON_MMIO_UAS
//#define NVKM_FALCON_MMIO_TRAP
#include "macros.fuc"
.section #nvd0_pwr_data
#define INCLUDE_PROC
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_PROC
#define INCLUDE_DATA
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_DATA
.align 256
.section #nvd0_pwr_code
#define INCLUDE_CODE
#include "kernel.fuc"
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_CODE
.align 256
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
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#ifndef __NVKM_PWR_OS_H__
#define __NVKM_PWR_OS_H__
/* Process names */
#define PROC_KERN 0x52544e49
#define PROC_IDLE 0x454c4449
#define PROC_HOST 0x54534f48
#define PROC_MEMX 0x584d454d
#define PROC_PERF 0x46524550
#define PROC_TEST 0x54534554
/* KERN: message identifiers */
#define KMSG_FIFO 0x00000000
#define KMSG_ALARM 0x00000001
/* MEMX: message identifiers */
#define MEMX_MSG_INFO 0
#define MEMX_MSG_EXEC 1
/* MEMX: script opcode definitions */
#define MEMX_ENTER 0
#define MEMX_LEAVE 1
#define MEMX_WR32 2
#define MEMX_WAIT 3
#define MEMX_DELAY 4
#endif
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc
0 → 100644
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifdef INCLUDE_PROC
process(PROC_PERF, #perf_init, #perf_recv)
#endif
/******************************************************************************
* PERF data segment
*****************************************************************************/
#ifdef INCLUDE_DATA
#endif
/******************************************************************************
* PERF code segment
*****************************************************************************/
#ifdef INCLUDE_CODE
// description
//
// $r15 - current (perf)
// $r14 - sender process name
// $r13 - message
// $r12 - data0
// $r11 - data1
// $r0 - zero
perf_recv:
ret
// description
//
// $r15 - current (perf)
// $r0 - zero
perf_init:
ret
#endif
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc
0 → 100644
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifdef INCLUDE_PROC
process(PROC_TEST, #test_init, #test_recv)
#endif
/******************************************************************************
* TEST data segment
*****************************************************************************/
#ifdef INCLUDE_DATA
#endif
/******************************************************************************
* TEST code segment
*****************************************************************************/
#ifdef INCLUDE_CODE
// description
//
// $r15 - current (test)
// $r14 - sender process name
// $r13 - message
// $r12 - data0
// $r11 - data1
// $r0 - zero
test_recv:
nv_iord($r1, NV_PPWR_DSCRATCH(2))
add b32 $r1 1
nv_iowr(NV_PPWR_DSCRATCH(2), $r1)
mov $r14 -0x2700 /* 0xd900, envyas grrr! */
sethi $r14 0x134f0000
call(timer)
ret
// description
//
// $r15 - current (test)
// $r0 - zero
test_init:
mov $r14 0x800
call(timer)
ret
#endif
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drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
0 → 100644
浏览文件 @
ff4b42c7
#ifndef __NVKM_PWR_MEMX_H__
#define __NVKM_PWR_MEMX_H__
#include <subdev/pwr.h>
#include <subdev/pwr/fuc/os.h>
struct
nouveau_memx
{
struct
nouveau_pwr
*
ppwr
;
u32
base
;
u32
size
;
struct
{
u32
mthd
;
u32
size
;
u32
data
[
64
];
}
c
;
};
static
void
memx_out
(
struct
nouveau_memx
*
memx
)
{
struct
nouveau_pwr
*
ppwr
=
memx
->
ppwr
;
int
i
;
if
(
memx
->
c
.
size
)
{
nv_wr32
(
ppwr
,
0x10a1c4
,
(
memx
->
c
.
size
<<
16
)
|
memx
->
c
.
mthd
);
for
(
i
=
0
;
i
<
memx
->
c
.
size
;
i
++
)
nv_wr32
(
ppwr
,
0x10a1c4
,
memx
->
c
.
data
[
i
]);
memx
->
c
.
size
=
0
;
}
}
static
void
memx_cmd
(
struct
nouveau_memx
*
memx
,
u32
mthd
,
u32
size
,
u32
data
[])
{
if
((
memx
->
c
.
size
+
size
>=
ARRAY_SIZE
(
memx
->
c
.
data
))
||
(
memx
->
c
.
size
&&
memx
->
c
.
mthd
!=
mthd
))
memx_out
(
memx
);
memcpy
(
&
memx
->
c
.
data
[
memx
->
c
.
size
],
data
,
size
*
sizeof
(
data
[
0
]));
memx
->
c
.
size
+=
size
;
memx
->
c
.
mthd
=
mthd
;
}
int
nouveau_memx_init
(
struct
nouveau_pwr
*
ppwr
,
struct
nouveau_memx
**
pmemx
)
{
struct
nouveau_memx
*
memx
;
u32
reply
[
2
];
int
ret
;
ret
=
ppwr
->
message
(
ppwr
,
reply
,
PROC_MEMX
,
MEMX_MSG_INFO
,
0
,
0
);
if
(
ret
)
return
ret
;
memx
=
*
pmemx
=
kzalloc
(
sizeof
(
*
memx
),
GFP_KERNEL
);
if
(
!
memx
)
return
-
ENOMEM
;
memx
->
ppwr
=
ppwr
;
memx
->
base
=
reply
[
0
];
memx
->
size
=
reply
[
1
];
/* acquire data segment access */
do
{
nv_wr32
(
ppwr
,
0x10a580
,
0x00000003
);
}
while
(
nv_rd32
(
ppwr
,
0x10a580
)
!=
0x00000003
);
nv_wr32
(
ppwr
,
0x10a1c0
,
0x01000000
|
memx
->
base
);
nv_wr32
(
ppwr
,
0x10a1c4
,
0x00010000
|
MEMX_ENTER
);
nv_wr32
(
ppwr
,
0x10a1c4
,
0x00000000
);
return
0
;
}
int
nouveau_memx_fini
(
struct
nouveau_memx
**
pmemx
,
bool
exec
)
{
struct
nouveau_memx
*
memx
=
*
pmemx
;
struct
nouveau_pwr
*
ppwr
=
memx
->
ppwr
;
u32
finish
,
reply
[
2
];
/* flush the cache... */
memx_out
(
memx
);
/* release data segment access */
nv_wr32
(
ppwr
,
0x10a1c4
,
0x00000000
|
MEMX_LEAVE
);
finish
=
nv_rd32
(
ppwr
,
0x10a1c0
)
&
0x00ffffff
;
nv_wr32
(
ppwr
,
0x10a580
,
0x00000000
);
/* call MEMX process to execute the script, and wait for reply */
if
(
exec
)
{
ppwr
->
message
(
ppwr
,
reply
,
PROC_MEMX
,
MEMX_MSG_EXEC
,
memx
->
base
,
finish
);
}
kfree
(
memx
);
return
0
;
}
void
nouveau_memx_wr32
(
struct
nouveau_memx
*
memx
,
u32
addr
,
u32
data
)
{
nv_debug
(
memx
->
ppwr
,
"R[%06x] = 0x%08x
\n
"
,
addr
,
data
);
memx_cmd
(
memx
,
MEMX_WR32
,
2
,
(
u32
[]){
addr
,
data
});
}
void
nouveau_memx_wait
(
struct
nouveau_memx
*
memx
,
u32
addr
,
u32
mask
,
u32
data
,
u32
nsec
)
{
nv_debug
(
memx
->
ppwr
,
"R[%06x] & 0x%08x == 0x%08x, %d us
\n
"
,
addr
,
mask
,
data
,
nsec
);
memx_cmd
(
memx
,
MEMX_WAIT
,
4
,
(
u32
[]){
addr
,
~
mask
,
data
,
nsec
});
memx_out
(
memx
);
/* fuc can't handle multiple */
}
void
nouveau_memx_nsec
(
struct
nouveau_memx
*
memx
,
u32
nsec
)
{
nv_debug
(
memx
->
ppwr
,
" DELAY = %d ns
\n
"
,
nsec
);
memx_cmd
(
memx
,
MEMX_DELAY
,
1
,
(
u32
[]){
nsec
});
memx_out
(
memx
);
/* fuc can't handle multiple */
}
#endif
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include "fuc/nv108.fuc.h"
struct
nv108_pwr_priv
{
struct
nouveau_pwr
base
;
};
static
int
nv108_pwr_ctor
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nouveau_object
**
pobject
)
{
struct
nv108_pwr_priv
*
priv
;
int
ret
;
ret
=
nouveau_pwr_create
(
parent
,
engine
,
oclass
,
&
priv
);
*
pobject
=
nv_object
(
priv
);
if
(
ret
)
return
ret
;
priv
->
base
.
code
.
data
=
nv108_pwr_code
;
priv
->
base
.
code
.
size
=
sizeof
(
nv108_pwr_code
);
priv
->
base
.
data
.
data
=
nv108_pwr_data
;
priv
->
base
.
data
.
size
=
sizeof
(
nv108_pwr_data
);
return
0
;
}
struct
nouveau_oclass
nv108_pwr_oclass
=
{
.
handle
=
NV_SUBDEV
(
PWR
,
0x00
),
.
ofuncs
=
&
(
struct
nouveau_ofuncs
)
{
.
ctor
=
nv108_pwr_ctor
,
.
dtor
=
_nouveau_pwr_dtor
,
.
init
=
_nouveau_pwr_init
,
.
fini
=
_nouveau_pwr_fini
,
},
};
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include "fuc/nva3.fuc.h"
struct
nva3_pwr_priv
{
struct
nouveau_pwr
base
;
};
static
int
nva3_pwr_init
(
struct
nouveau_object
*
object
)
{
struct
nva3_pwr_priv
*
priv
=
(
void
*
)
object
;
nv_mask
(
priv
,
0x022210
,
0x00000001
,
0x00000000
);
nv_mask
(
priv
,
0x022210
,
0x00000001
,
0x00000001
);
return
nouveau_pwr_init
(
&
priv
->
base
);
}
static
int
nva3_pwr_ctor
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nouveau_object
**
pobject
)
{
struct
nva3_pwr_priv
*
priv
;
int
ret
;
ret
=
nouveau_pwr_create
(
parent
,
engine
,
oclass
,
&
priv
);
*
pobject
=
nv_object
(
priv
);
if
(
ret
)
return
ret
;
priv
->
base
.
code
.
data
=
nva3_pwr_code
;
priv
->
base
.
code
.
size
=
sizeof
(
nva3_pwr_code
);
priv
->
base
.
data
.
data
=
nva3_pwr_data
;
priv
->
base
.
data
.
size
=
sizeof
(
nva3_pwr_data
);
return
0
;
}
struct
nouveau_oclass
nva3_pwr_oclass
=
{
.
handle
=
NV_SUBDEV
(
PWR
,
0xa3
),
.
ofuncs
=
&
(
struct
nouveau_ofuncs
)
{
.
ctor
=
nva3_pwr_ctor
,
.
dtor
=
_nouveau_pwr_dtor
,
.
init
=
nva3_pwr_init
,
.
fini
=
_nouveau_pwr_fini
,
},
};
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include "fuc/nvc0.fuc.h"
struct
nvc0_pwr_priv
{
struct
nouveau_pwr
base
;
};
static
int
nvc0_pwr_ctor
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nouveau_object
**
pobject
)
{
struct
nvc0_pwr_priv
*
priv
;
int
ret
;
ret
=
nouveau_pwr_create
(
parent
,
engine
,
oclass
,
&
priv
);
*
pobject
=
nv_object
(
priv
);
if
(
ret
)
return
ret
;
priv
->
base
.
code
.
data
=
nvc0_pwr_code
;
priv
->
base
.
code
.
size
=
sizeof
(
nvc0_pwr_code
);
priv
->
base
.
data
.
data
=
nvc0_pwr_data
;
priv
->
base
.
data
.
size
=
sizeof
(
nvc0_pwr_data
);
return
0
;
}
struct
nouveau_oclass
nvc0_pwr_oclass
=
{
.
handle
=
NV_SUBDEV
(
PWR
,
0xc0
),
.
ofuncs
=
&
(
struct
nouveau_ofuncs
)
{
.
ctor
=
nvc0_pwr_ctor
,
.
dtor
=
_nouveau_pwr_dtor
,
.
init
=
_nouveau_pwr_init
,
.
fini
=
_nouveau_pwr_fini
,
},
};
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
0 → 100644
浏览文件 @
ff4b42c7
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include "fuc/nvd0.fuc.h"
struct
nvd0_pwr_priv
{
struct
nouveau_pwr
base
;
};
static
int
nvd0_pwr_ctor
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nouveau_object
**
pobject
)
{
struct
nvd0_pwr_priv
*
priv
;
int
ret
;
ret
=
nouveau_pwr_create
(
parent
,
engine
,
oclass
,
&
priv
);
*
pobject
=
nv_object
(
priv
);
if
(
ret
)
return
ret
;
priv
->
base
.
code
.
data
=
nvd0_pwr_code
;
priv
->
base
.
code
.
size
=
sizeof
(
nvd0_pwr_code
);
priv
->
base
.
data
.
data
=
nvd0_pwr_data
;
priv
->
base
.
data
.
size
=
sizeof
(
nvd0_pwr_data
);
return
0
;
}
struct
nouveau_oclass
nvd0_pwr_oclass
=
{
.
handle
=
NV_SUBDEV
(
PWR
,
0xd0
),
.
ofuncs
=
&
(
struct
nouveau_ofuncs
)
{
.
ctor
=
nvd0_pwr_ctor
,
.
dtor
=
_nouveau_pwr_dtor
,
.
init
=
_nouveau_pwr_init
,
.
fini
=
_nouveau_pwr_fini
,
},
};
This diff is collapsed.
Click to expand it.
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