ARM: dts: sunxi: reference: Move the muxing back to the common DTSI

Now that all the SoCs using the tablet reference design DTSI are using the
same pinctrl naming scheme, we can move back the pinctrl phandles to the
main DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi

@@ -76,8 +76,6 @@
 };
 
 &i2c0 {
-	pinctrl-0 = <&i2c0_pins>;
-
 	axp209: pmic@34 {
 		reg = <0x34>;
 		interrupts = <0>;
@@ -85,8 +83,6 @@
 };
 
 &i2c1 {
-	pinctrl-0 = <&i2c1_pins>;
-
 	/*
 	 * The gsl1680 is rated at 400KHz and it will not work reliable at
 	 * 100KHz, this has been confirmed on multiple different q8 tablets.
@@ -150,10 +146,6 @@
 	};
 };
 
-&pwm {
-	pinctrl-0 = <&pwm0_pin>;
-};
-
 &reg_dcdc2 {
 	regulator-always-on;
 	regulator-min-microvolt = <1000000>;

arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi

@@ -62,7 +62,6 @@
 };
 
 &i2c0 {
-	pinctrl-0 = <&i2c0_pins>;
 	/*
 	 * The gsl1680 is rated at 400KHz and it will not work reliable at
 	 * 100KHz, this has been confirmed on multiple different q8 tablets.
@@ -80,10 +79,6 @@
 	};
 };
 
-&i2c1 {
-	pinctrl-0 = <&i2c1_pins>;
-};
-
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
@@ -101,10 +96,6 @@
 	};
 };
 
-&pwm {
-	pinctrl-0 = <&pwm0_pin>;
-};
-
 &r_rsb {
 	status = "okay";
 

arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi

@@ -46,13 +46,13 @@
 
 &i2c0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
+	pinctrl-0 = <&i2c0_pins>;
 	status = "okay";
 };
 
 &i2c1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_a>;
+	pinctrl-0 = <&i2c1_pins>;
 	status = "okay";
 };
 
@@ -77,6 +77,6 @@
 
 &pwm {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pwm0_pins>;
+	pinctrl-0 = <&pwm0_pin>;
 	status = "okay";
 };