Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openeuler
Kernel
提交
f82c44a7
K
Kernel
项目概览
openeuler
/
Kernel
接近 2 年 前同步成功
通知
8
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
K
Kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
提交
f82c44a7
编写于
1月 08, 2014
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nve0/fifo: s/playlist/runlist/
As per Android GK20A driver. Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
f76dd80f
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
20 addition
and
14 deletion
+20
-14
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+20
-14
未找到文件。
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
浏览文件 @
f82c44a7
...
...
@@ -57,8 +57,8 @@ static const struct {
#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
struct
nve0_fifo_engn
{
struct
nouveau_gpuobj
*
play
list
[
2
];
int
cur_
play
list
;
struct
nouveau_gpuobj
*
run
list
[
2
];
int
cur_
run
list
;
};
struct
nve0_fifo_priv
{
...
...
@@ -87,7 +87,7 @@ struct nve0_fifo_chan {
******************************************************************************/
static
void
nve0_fifo_
play
list_update
(
struct
nve0_fifo_priv
*
priv
,
u32
engine
)
nve0_fifo_
run
list_update
(
struct
nve0_fifo_priv
*
priv
,
u32
engine
)
{
struct
nouveau_bar
*
bar
=
nouveau_bar
(
priv
);
struct
nve0_fifo_engn
*
engn
=
&
priv
->
engine
[
engine
];
...
...
@@ -96,8 +96,8 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
int
i
,
p
;
mutex_lock
(
&
nv_subdev
(
priv
)
->
mutex
);
cur
=
engn
->
playlist
[
engn
->
cur_play
list
];
engn
->
cur_
playlist
=
!
engn
->
cur_play
list
;
cur
=
engn
->
runlist
[
engn
->
cur_run
list
];
engn
->
cur_
runlist
=
!
engn
->
cur_run
list
;
for
(
i
=
0
,
p
=
0
;
i
<
priv
->
base
.
max
;
i
++
)
{
u32
ctrl
=
nv_rd32
(
priv
,
0x800004
+
(
i
*
8
))
&
0x001f0001
;
...
...
@@ -112,7 +112,7 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
nv_wr32
(
priv
,
0x002270
,
cur
->
addr
>>
12
);
nv_wr32
(
priv
,
0x002274
,
(
engine
<<
20
)
|
(
p
>>
3
));
if
(
!
nv_wait
(
priv
,
0x002284
+
(
engine
*
4
),
0x00100000
,
0x00000000
))
nv_error
(
priv
,
"
play
list %d update timeout
\n
"
,
engine
);
nv_error
(
priv
,
"
run
list %d update timeout
\n
"
,
engine
);
mutex_unlock
(
&
nv_subdev
(
priv
)
->
mutex
);
}
...
...
@@ -279,7 +279,7 @@ nve0_fifo_chan_init(struct nouveau_object *object)
nv_mask
(
priv
,
0x800004
+
(
chid
*
8
),
0x000f0000
,
chan
->
engine
<<
16
);
nv_wr32
(
priv
,
0x800000
+
(
chid
*
8
),
0x80000000
|
base
->
addr
>>
12
);
nv_mask
(
priv
,
0x800004
+
(
chid
*
8
),
0x00000400
,
0x00000400
);
nve0_fifo_
play
list_update
(
priv
,
chan
->
engine
);
nve0_fifo_
run
list_update
(
priv
,
chan
->
engine
);
nv_mask
(
priv
,
0x800004
+
(
chid
*
8
),
0x00000400
,
0x00000400
);
return
0
;
}
...
...
@@ -292,7 +292,7 @@ nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
u32
chid
=
chan
->
base
.
chid
;
nv_mask
(
priv
,
0x800004
+
(
chid
*
8
),
0x00000800
,
0x00000800
);
nve0_fifo_
play
list_update
(
priv
,
chan
->
engine
);
nve0_fifo_
run
list_update
(
priv
,
chan
->
engine
);
nv_wr32
(
priv
,
0x800000
+
(
chid
*
8
),
0x00000000
);
return
nouveau_fifo_channel_fini
(
&
chan
->
base
,
suspend
);
...
...
@@ -544,8 +544,14 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
}
if
(
stat
&
0x40000000
)
{
nv_warn
(
priv
,
"unknown status 0x40000000
\n
"
);
nv_mask
(
priv
,
0x002a00
,
0x00000000
,
0x00000000
);
u32
mask
=
nv_mask
(
priv
,
0x002a00
,
0x00000000
,
0x00000000
);
while
(
mask
)
{
u32
engn
=
ffs
(
mask
)
-
1
;
/* runlist event, not currently used */
mask
&=
~
(
1
<<
engn
);
}
stat
&=
~
0x40000000
;
}
...
...
@@ -616,8 +622,8 @@ nve0_fifo_dtor(struct nouveau_object *object)
nouveau_gpuobj_ref
(
NULL
,
&
priv
->
user
.
mem
);
for
(
i
=
0
;
i
<
FIFO_ENGINE_NR
;
i
++
)
{
nouveau_gpuobj_ref
(
NULL
,
&
priv
->
engine
[
i
].
play
list
[
1
]);
nouveau_gpuobj_ref
(
NULL
,
&
priv
->
engine
[
i
].
play
list
[
0
]);
nouveau_gpuobj_ref
(
NULL
,
&
priv
->
engine
[
i
].
run
list
[
1
]);
nouveau_gpuobj_ref
(
NULL
,
&
priv
->
engine
[
i
].
run
list
[
0
]);
}
nouveau_fifo_destroy
(
&
priv
->
base
);
...
...
@@ -640,12 +646,12 @@ nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
for
(
i
=
0
;
i
<
FIFO_ENGINE_NR
;
i
++
)
{
ret
=
nouveau_gpuobj_new
(
nv_object
(
priv
),
NULL
,
0x8000
,
0x1000
,
0
,
&
priv
->
engine
[
i
].
play
list
[
0
]);
0
,
&
priv
->
engine
[
i
].
run
list
[
0
]);
if
(
ret
)
return
ret
;
ret
=
nouveau_gpuobj_new
(
nv_object
(
priv
),
NULL
,
0x8000
,
0x1000
,
0
,
&
priv
->
engine
[
i
].
play
list
[
1
]);
0
,
&
priv
->
engine
[
i
].
run
list
[
1
]);
if
(
ret
)
return
ret
;
}
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录