EDAC/i10nm: Add Intel Emerald Rapids server support

mainline inclusion
from mainline-v6.3-rc1
commit e4b2bc66
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I7DZRN
CVE: NA

Intel-SIG: commit e4b2bc66 EDAC/i10nm: Add Intel Emerald Rapids server support.
Backport to decode memory error for Intel Emerald Rapids server.

--------------------------------

The Emerald Rapids CPU model uses similar memory controller registers
as Sapphire Rapids server. Add Emerald Rapids CPU model number ID for
EDAC support.
Tested-by: NLi Zhang <li4.zhang@intel.com>
Signed-off-by: NQiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: NTony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/all/20230113032802.41752-1-qiuxu.zhuo@intel.com
[ Youquan Song: amend commit log ]
Signed-off-by: NYouquan Song <youquan.song@intel.com>
(cherry picked from commit 6b1c0854)

drivers/edac/i10nm_base.c

@@ -674,6 +674,7 @@ static const struct x86_cpu_id i10nm_cpuids[] = {
 	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,		X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
 	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D,		X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
 	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X,	X86_STEPPINGS(0x0, 0xf), &spr_cfg),
+	X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(EMERALDRAPIDS_X,	X86_STEPPINGS(0x0, 0xf), &spr_cfg),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);