提交 f3448b21 编写于 作者: T Thomas Gleixner 提交者: Lin Wang

x86/fpu: Move mxcsr related code to core

mainline inclusion
from mainline-v5.16-rc1
commit d9d005f3
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I590ZC
CVE: NA

Intel-SIG: commit d9d005f3 x86/fpu: Move mxcsr related code to core.

--------------------------------

No need to expose that to code which only needs the XCR0 accessors.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20211015011539.740012411@linutronix.deSigned-off-by: NLin Wang <lin.x.wang@intel.com>
上级 3e7b801e
......@@ -2,17 +2,6 @@
#ifndef _ASM_X86_FPU_XCR_H
#define _ASM_X86_FPU_XCR_H
/*
* MXCSR and XCR definitions:
*/
static inline void ldmxcsr(u32 mxcsr)
{
asm volatile("ldmxcsr %0" :: "m" (mxcsr));
}
extern unsigned int mxcsr_feature_mask;
#define XCR_XFEATURE_ENABLED_MASK 0x00000000
static inline u64 xgetbv(u32 index)
......
......@@ -11,6 +11,7 @@
#include <linux/init.h>
#include "internal.h"
#include "legacy.h"
/*
* Initialize the registers found in all CPUs, CR0 and CR4:
......
......@@ -4,6 +4,13 @@
#include <asm/fpu/types.h>
extern unsigned int mxcsr_feature_mask;
static inline void ldmxcsr(u32 mxcsr)
{
asm volatile("ldmxcsr %0" :: "m" (mxcsr));
}
/*
* Returns 0 on success or the trap number when the operation raises an
* exception.
......
......@@ -12,6 +12,7 @@
#include "context.h"
#include "internal.h"
#include "legacy.h"
/*
* The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
......
......@@ -14,8 +14,9 @@
#include <asm/fpu/api.h>
#include <asm/fpu/internal.h>
#include <asm/fpu/signal.h>
#include <asm/fpu/regset.h>
#include <asm/fpu/signal.h>
#include <asm/fpu/xcr.h>
#include <asm/tlbflush.h>
......
......@@ -16,6 +16,7 @@
#include <linux/swap.h>
#include <asm/pkru.h>
#include <asm/fpu/xcr.h>
#include "x86.h"
#include "svm.h"
......
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