提交 ed160672 编写于 作者: S Sandeep Paulraj 提交者: Kevin Hilman

DaVinci: DM365: Correct USB parent clock

The parent clock for the USB source clock is actually PLL1 aux clock,
not PLL2 sysclk1.
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
上级 eb5ba378
......@@ -369,7 +369,7 @@ static struct clk timer3_clk = {
static struct clk usb_clk = {
.name = "usb",
.parent = &pll2_sysclk1,
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_USB,
};
......
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