drm/i915: disable the infoframe before changing it

That's what the VIDEO_DIP_CTL documentation says we need to do. Except
when it's the AVI InfoFrame and we're ironlake_write_infoframe.
Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_hdmi.c

@@ -153,6 +153,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 	val |= intel_infoframe_index(frame);
 
+	val &= ~intel_infoframe_enable(frame);
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(VIDEO_DIP_CTL, val);
@@ -185,6 +186,13 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 	val |= intel_infoframe_index(frame);
 
+	/* The DIP control register spec says that we need to update the AVI
+	 * infoframe without clearing its enable bit */
+	if (frame->type == DIP_TYPE_AVI)
+		val |= VIDEO_DIP_ENABLE_AVI;
+	else
+		val &= ~intel_infoframe_enable(frame);
+
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(reg, val);
@@ -217,6 +225,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 	val |= intel_infoframe_index(frame);
 
+	val &= ~intel_infoframe_enable(frame);
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(reg, val);