drm/amd/display/dc: add DCE_VERSION for DCE8 APUs

DCE 8.1 = Kaveri
DCE 8.3 = Kabini/Mullins
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

@@ -37,6 +37,8 @@ bool dal_bios_parser_init_cmd_tbl_helper(
 {
 	switch (dce) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 		*h = dal_cmd_tbl_helper_dce80_get_table();
 		return true;
 

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

@@ -39,6 +39,8 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
 {
 	switch (dce) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 		*h = dal_cmd_tbl_helper_dce80_get_table();
 		return true;
 

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

@@ -50,9 +50,16 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 	switch (asic_id.chip_family) {
 
 	case FAMILY_CI:
-	case FAMILY_KV:
 		dc_version = DCE_VERSION_8_0;
 		break;
+	case FAMILY_KV:
+		if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
+		    ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
+		    ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
+			dc_version = DCE_VERSION_8_3;
+		else
+			dc_version = DCE_VERSION_8_1;
+		break;
 	case FAMILY_CZ:
 		dc_version = DCE_VERSION_11_0;
 		break;
@@ -94,6 +101,8 @@ struct resource_pool *dc_create_resource_pool(
 
 	switch (dc_version) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 		res_pool = dce80_create_resource_pool(
 			num_virtual_links, dc);
 		break;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

@@ -578,6 +578,8 @@ static uint32_t dce110_get_pix_clk_dividers(
 
 	switch (cs->ctx->dce_version) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 	case DCE_VERSION_10_0:
 	case DCE_VERSION_11_0:
 		pll_calc_error =
@@ -862,6 +864,8 @@ static bool dce110_program_pix_clk(
 
 	switch (clock_source->ctx->dce_version) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 	case DCE_VERSION_10_0:
 	case DCE_VERSION_11_0:
 		bp_pc_params.reference_divider = pll_settings->reference_divider;
@@ -1209,6 +1213,8 @@ bool dce110_clk_src_construct(
 
 	switch (clk_src->base.ctx->dce_version) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 	case DCE_VERSION_10_0:
 	case DCE_VERSION_11_0:
 

drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c

@@ -66,6 +66,8 @@ bool dal_hw_factory_init(
 
 	switch (dce_version) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 		dal_hw_factory_dce80_init(factory);
 		return true;
 

drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c

@@ -65,6 +65,8 @@ bool dal_hw_translate_init(
 
 	switch (dce_version) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 		dal_hw_translate_dce80_init(translate);
 		return true;
 	case DCE_VERSION_10_0:

drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c

@@ -79,6 +79,8 @@ struct i2caux *dal_i2caux_create(
 
 	switch (ctx->dce_version) {
 	case DCE_VERSION_8_0:
+	case DCE_VERSION_8_1:
+	case DCE_VERSION_8_3:
 		return dal_i2caux_dce80_create(ctx);
 	case DCE_VERSION_11_2:
 		return dal_i2caux_dce112_create(ctx);

drivers/gpu/drm/amd/display/include/dal_types.h

@@ -35,6 +35,8 @@ struct dc_bios;
 enum dce_version {
 	DCE_VERSION_UNKNOWN = (-1),
 	DCE_VERSION_8_0,
+	DCE_VERSION_8_1,
+	DCE_VERSION_8_3,
 	DCE_VERSION_10_0,
 	DCE_VERSION_11_0,
 	DCE_VERSION_11_2,